Commit 84e93daa26 ("freedreno/registers: allow skipping the
validation") synced a change that made validation optional for
kernel builds, to avoid a lxml dependency for kernel builds.
But this inadvertantly also disabled schema validation on the
mesa side. CI (and meson "test" target) still validates the
xml against the schema, but it is easier if this is also done
as part of the normal build to avoid suprises from Marge.
Fixes: 84e93daa26 ("freedreno/registers: allow skipping the validation")
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37216>
(cherry picked from commit a70279adc2)
The attachment loadOp for stencil buffers is not stored at
attachment->desc.loadOp. It is stored at attachment->desc.stencilLoadOp
so v3dv was ignoring the clear values for stencil if the depth buffer
wasn't setup with the VK_ATTACHMENT_LOAD_OP_CLEAR.
Fixes: 4d0e497a3e ("v3dv: implement support for depth testing")
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37228>
(cherry picked from commit 914b60f0dd)
When disassembling and BRW IR is available (which happens in the
generator), there will be pointers to the BRW's basic block structures
that are used to print the block numbers and predecessor/successors
in the output.
There are two challenges:
- Because DO and FLOW instructions are not real instructions, they are
not emitted in the output but would still cause the output to contain
empty blocks. Previous code accounted for DO but still had problems.
- DO blocks have special physical links that don't make sense when the
DO is not emitted at the end, but they would be shown even if that
block was omitted.
These issues can be seen here (edited to remove non-essential bits)
```
START B0 (2 cycles)
mov(8) g126<1>UD 0x3f800000UD
END B0 ->B1
START B2 <-B1 <-B4 (0 cycles)
END B2 ->B3
START B3 <-B2 (260 cycles)
LABEL1:
mov(8) g1<1>D 0D
cmp.ge.f0.0(8) null<1>D g2<0,1,0>D 10D
sync nop(1) null<0,1,0>UB
send(1) g0UD g1UD nullUD
(+f0.0) break(8) JIP: LABEL0 UIP: LABEL0
END B3 ->B1 ->B5 ->B4
START B4 <-B3 (1000 cycles)
sync nop(1) null<0,1,0>UB
mov(8) g126<1>UD g0<0,1,0>UD
LABEL0:
while(8) JIP: LABEL1
END B4 ->B2
START B5 <-B1 <-B3 (20 cycles)
```
For example:
- Block 1 is missing (a skipped DO block)
- Block 2 is empty (it was a FLOW block)
- Block 3 ends with a link to Block 1 (the special links involving DO
blocks).
Two key changes were made to fix this. First, skip the DO and FLOW
blocks completely. The use_tail ensures that the instruction group is
reused to avoid empty blocks. Second, when printing, the successors and
predecessors, walk through the skipped blocks. And finally, don't print
the special blocks.
With the fix, here's the output. Note the blocks retain their original
BRW IR number.
```
START B0 (2 cycles)
mov(8) g127<1>UD 0x3f800000UD
END B0 ->B3
START B3 <-B0 <-B4 (260 cycles)
LABEL1:
mov(8) g1<1>D 0D
cmp.ge.f0.0(8) null<1>D g2<0,1,0>D 10D
sync nop(1) null<0,1,0>UB
send(1) g0UD g1UD nullUD
(+f0.0) break(8) JIP: LABEL0 UIP: LABEL0
END B3 ->B5 ->B4
START B4 <-B3 (1000 cycles)
sync nop(1) null<0,1,0>UB
mov(8) g127<1>UD g0<0,1,0>UD
LABEL0:
while(8) JIP: LABEL1
END B4 ->B3
START B5 <-B3 (20 cycles)
```
Issue was spotted by Ken.
Fixes: d2c39b1779 ("intel/brw: Always have a (non-DO) block after a DO in the CFG")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36226>
(cherry picked from commit f37c9c873c)
This is an optimization, but it also seems to be required because the HW
sometimes fails to set ViewIndex to 0. This fixes flakes with
dEQP-VK.renderpass2.fragment_density_map.*multiviewport where the VS for
the main renderpass is reused for the copy renderpass afterwards and it
copies ViewIndex to ViewportIndex expecting it to be 0 since multiview
is disabled for the copy renderpass.
Closes: #13534
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37206>
(cherry picked from commit 7527ad001a)
Partial results should be computed for all types of queries.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36916>
(cherry picked from commit 262baafe27)
The definitive linux kernel counterpart update is now merged.
The linux kernel commit dc5c742f41c0a1c2b14e4357c752851e015f3bcd
(v6.17-rc1) set the new r600 drm version requirement. This change
updates the drm version accordingly to 2.51.0.
Fixes: 9e1180b335 ("r600: implement ARB_indirect_parameters")
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37118>
(cherry picked from commit ef01013b71)
The function resource_copy_region is expected to have a memcpy()
like behavior. Some formats, like r11g11b10_float, do not preserve
the original raw values. This was the problem. This change
updates r600_resource_copy_region() to use the generic copy path
for those formats.
This change takes into account how 8235d3aa19 "radeonsi: preserve
NaNs in draw-based resource_copy_region" proceeds.
This change fixes the remaining khr-gl and deqp-gles31 copy_image tests. This
change was tested on palm, barts and cayman. Here are the tests fixed:
khr-gl4[2-6]/texture_view/view_classes: fail pass
khr-gl4[3-6]/copy_image/functional_src_target_texture_2d_array_src_format_rgb9_e5_dst_target_texture_2d_array_dst_format_r11f_g11f_b10f: fail pass
khr-gl4[3-6]/copy_image/functional_src_target_texture_2d_array_src_format_rgb9_e5_dst_target_texture_3d_dst_format_r11f_g11f_b10f: fail pass
khr-gl4[3-6]/copy_image/functional_src_target_texture_2d_array_src_format_rgb9_e5_dst_target_texture_rectangle_dst_format_r11f_g11f_b10f: fail pass
khr-gl4[3-6]/copy_image/functional_src_target_texture_3d_src_format_rgb9_e5_dst_target_texture_2d_array_dst_format_r11f_g11f_b10f: fail pass
khr-gl4[3-6]/copy_image/functional_src_target_texture_3d_src_format_rgb9_e5_dst_target_texture_3d_dst_format_r11f_g11f_b10f: fail pass
khr-gl4[3-6]/copy_image/functional_src_target_texture_3d_src_format_rgb9_e5_dst_target_texture_rectangle_dst_format_r11f_g11f_b10f: fail pass
khr-gl4[3-6]/copy_image/functional_src_target_texture_rectangle_src_format_rgb9_e5_dst_target_texture_2d_array_dst_format_r11f_g11f_b10f: fail pass
khr-gl4[3-6]/copy_image/functional_src_target_texture_rectangle_src_format_rgb9_e5_dst_target_texture_3d_dst_format_r11f_g11f_b10f: fail pass
khr-gl4[3-6]/copy_image/functional_src_target_texture_rectangle_src_format_rgb9_e5_dst_target_texture_rectangle_dst_format_r11f_g11f_b10f: fail pass
deqp-gles31/functional/copy_image/non_compressed/viewclass_16_bits/.*: fail pass
deqp-gles31/functional/copy_image/non_compressed/viewclass_32_bits/.*: fail pass
Cc: mesa-stable
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37117>
(cherry picked from commit df5e8e1252)
If we never get rate control info, we would treat it as rate control
disabled and use QP value from slice info which is always 0 for default
rate control.
Cc: mesa-stable
Reviewed-by: Autumn Ashton <misyl@froggi.es>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37156>
(cherry picked from commit a03e055cd3)
Check if allocation is large enough to hold the
linear and gc contexts before probing for them.
Fixes: 7b5b164281 ("util: Add function print information about a ralloc tree")
Acked-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37017>
(cherry picked from commit 62815cc91f)
it's otherwise possible for this to race and hit the draw before
precompile finishes without ever waiting on the fence
I guess this just worked coincidentally before?
cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37197>
(cherry picked from commit 6596bf69c6)
This is supported and must be enabled when
descriptorBinding*UpdateAfterBind is active.
Fixes the following VVL error:
Validation Error: [ VUID-VkDeviceCreateInfo-robustBufferAccess-10247 ]
vkCreateDevice(): robustBufferAccessUpdateAfterBind is false, but both
robustBufferAccess and a descriptorBinding*UpdateAfterBind feature are
enabled.
Fixes: d9fcf5de55 ("turnip: Enable nonuniform descriptor indexing")
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36787>
(cherry picked from commit 31f6235126)
EOS events are buggy on GFX7 and can cause hangs when used
together in the same IB with CP DMA packets that use L2.
While we don't use the L2 for CP DMA copies, we still use it
with CP DMA prefetches, so the issue needs to be mitigated.
As a mitigation, avoid using EVENT_WRITE_EOS and prefer to use
the BOTTOM_OF_PIPE event instead of PS_DONE/CS_DONE, which should
be close enough.
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37121>
(cherry picked from commit c56c746b71)
GFX6 actually supports IB2, but doesn't support chaining between
chunks inside the IB2. See WaCpIb2ChainingUnsupported in PAL.
Disable IB2 on GFX6 for now.
The proper fix will be to disable use_ib in just secondary
command buffers on GFX6 and emit multiple IB2 packets in the
main command buffer. This will be implemented later.
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37121>
(cherry picked from commit e8d1e935fb)
After a refactor last year, the noibs option stopped working
because it hits an assertion when empty IBs are submitted.
Emit a single large NOP packet to avoid submitting empty IBs.
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37121>
(cherry picked from commit 132a61c6b7)
The hardware actually compares a pair of 64-bit values, rather than
comparing a single value against zero like we previously assumed.
This wasn't an issue in most cases before because if the buffer is
zero-initialized the previous code happens to work. If we get a
buffer with garbage in it though we would run into issues.
Fixes: 80eac1337d ("nvk: Always copy conditional rendering value before compare")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13821
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Mary Guillemard <mary@mary.zone>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37153>
(cherry picked from commit 90ac7d13dc)
nvk_cmd_pool_free_gart_mem_list frees this buffer, so we need to clear
the pointers to it in order to avoid a use after free.
Fixes: 07c70c77de ("nvk: add cond render upload buffer.")
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Mary Guillemard <mary@mary.zone>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37153>
(cherry picked from commit eaa547f6f2)
The vulkan spec says that we should ignore memoryOffset when
VkBindImageMemorySwapchainInfoKHR is present. wsi common assumes that we
bind the wsi image at offset 0, so set the offset to 0. This change
aligns with common wsi, and also obeys dedicated alloc requirement.
Fixes: f887116c49 ("turnip: adopt wsi_common_get_memory")
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37099>
(cherry picked from commit cef48af271)
Fixes: 5f757bb95c ("nir: Make the load_store_vectorizer provide align_mul + align_offset.")
This is found when I am trying to narrow bit_size and num_components to uint8_t
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37042>
(cherry picked from commit 949a056934)
We were testing some conditions in the wrong order, so spilled
registers were being printed as if they were uniforms. This is
incorrect, but only subtly so, and lead to confusion.
Fixes: 6c64ad934f ("panfrost: spill registers in SSA form")
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Ashley Smith <ashley.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37092>
(cherry picked from commit e3552c427e)
The intention of the code was to allow PHI values to be propagated
if they were in registers (as opposed to in memory). As written though
values were never propagated. I think this typo was due to some
debug code that wasn't removed properly.
Fixes: 6c64ad934f ("panfrost: spill registers in SSA form")
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Ashley Smith <ashley.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37092>
(cherry picked from commit d482b6ca68)
Secondary command buffers with RENDER_PASS_CONTINUE_BIT don't reset
rp_trace, and without reset we get garbage tracepoints.
Fixes garbage sysmem_clear_all tracepoints in some games running
though DXVK.
Fixes: 630380349b ("tu: Give renderpass events a separate trace buffer")
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37161>
(cherry picked from commit 482e0d0d1e)
These two properties reports how the interaction between MSAA coverage
and occlusion queries works. We need to report the correct value here,
otherwise applications might misbehave.
Fixes: 5ee3c10d1e ("panvk: advertise vulkan 1.4 on v10+")
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37136>
(cherry picked from commit 166d650c10)
The non-compute end flag should be INTEL_DS_TRACEPOINT_FLAG_END_OF_PIPE.
This fixes the broken anv utrace for anything non-compute that can
potentially overlap (execute in parallel).
Fixes: 6281b207db ("anv: add tracepoints timestamp mode for empty dispatches")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37155>
(cherry picked from commit c0e51bcf24)
ENABLE_DRM_AMDGPU must be defined when amdgpu_virtio is enabled;
otherwise, vdrm and amdgpu_virtio will have different definitions of
struct virgl_renderer_capset_drm. As a result, on amdgpu_virtio side,
the content of struct vdrm_device will be corrupted.
Thanks Honglei Huang <honglei1.huang@amd.com> for pointing out the
different definitions of struct virgl_renderer_capset_drm.
Cc: mesa-stable
Signed-off-by: Trigger Huang <Trigger.Huang@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37023>
(cherry picked from commit 5736280730)
