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r600: implement ARB_indirect_parameters
This change extends the ARB_shader_draw_parameters algorithm to support ARB_indirect_parameters. The linux kernel needs to be updated to support the following PM4 commands: COND_EXEC and COND_WRITE. Without the update, this extension is disabled. This change was tested on cypress, palm, barts and cayman. It passes all the piglit tests (6/6) and all the khr-gl45 tests (3/3). Signed-off-by: Patrick Lerda <patrick9876@free.fr> Reviewed-by: Gert Wollny <gert.wollny@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34726>
This commit is contained in:
Patrick Lerda
Marge Bot
parent
f66f5d1cd5
commit
9e1180b335
3 changed files with 378 additions and 15 deletions
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@ -228,7 +228,7 @@ GL 4.5, GLSL 4.50 -- all DONE: freedreno/a6xx, nvc0, r600, radeonsi, llvmpipe, v
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GL 4.6, GLSL 4.60 -- all DONE: radeonsi, virgl, zink, iris, crocus/gen7+, d3d12, asahi
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GL_ARB_gl_spirv DONE (freedreno, llvmpipe)
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GL_ARB_indirect_parameters DONE (freedreno/a6xx+, nvc0, llvmpipe, virgl)
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GL_ARB_indirect_parameters DONE (freedreno/a6xx+, nvc0, llvmpipe, virgl, r600/evergreen+)
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GL_ARB_pipeline_statistics_query DONE (freedreno/a6xx+, nvc0, r600, llvmpipe, softpipe, crocus/gen6+)
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GL_ARB_polygon_offset_clamp DONE (freedreno, nv50, nvc0, r600, llvmpipe, v3d, panfrost, crocus)
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GL_ARB_shader_atomic_counter_ops DONE (freedreno/a5xx+, nvc0, r600, llvmpipe, softpipe, v3d, panfrost)
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@ -24,6 +24,7 @@
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#include "radeon_video.h"
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#include "radeon_uvd.h"
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#include "util/os_time.h"
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#include "util/libdrm.h"
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static const struct debug_named_value r600_debug_options[] = {
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/* features */
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@ -361,9 +362,33 @@ static void r600_init_compute_caps(struct r600_screen *screen)
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caps->max_variable_threads_per_block = R600_MAX_VARIABLE_THREADS_PER_BLOCK;
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}
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static inline unsigned
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r600_version_simple(const unsigned version_major,
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const unsigned version_minor,
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const unsigned version_patchlevel)
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{
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return version_major * 1000000 +
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version_minor * 1000 +
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version_patchlevel;
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}
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static inline unsigned
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r600_get_drm_version(struct r600_screen *rscreen)
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{
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drmVersionPtr version = drmGetVersion(rscreen->b.ws->get_fd(rscreen->b.ws));
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const unsigned drm_version = r600_version_simple(version->version_major,
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version->version_minor,
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version->version_patchlevel);
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drmFreeVersion(version);
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return drm_version;
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}
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static void r600_init_screen_caps(struct r600_screen *rscreen)
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{
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struct pipe_caps *caps = (struct pipe_caps *)&rscreen->b.b.caps;
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const unsigned drm_version = r600_get_drm_version(rscreen);
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u_init_pipe_screen_caps(&rscreen->b.b, 1);
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@ -481,6 +506,8 @@ static void r600_init_screen_caps(struct r600_screen *rscreen)
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caps->multi_draw_indirect_partial_stride =
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caps->multi_draw_indirect =
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caps->draw_parameters = family >= CHIP_CEDAR;
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caps->multi_draw_indirect_params = family >= CHIP_CEDAR &&
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drm_version >= r600_version_simple(2, 50, 1);
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caps->buffer_sampler_view_rgba_only = family < CHIP_CEDAR;
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@ -2214,6 +2214,295 @@ r600_draw_indirect(struct r600_context *rctx,
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assert(radeon_check_cs(rctx, cs) == R600_DRAW_PARAMETERS_DRAW_INDIRECT_CS);
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}
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#ifndef PKT3_EVENT_WRITE_EOS
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#define PKT3_EVENT_WRITE_EOS 0x48
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#endif
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#ifndef EVENT_TYPE_PS_DONE
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#define EVENT_TYPE_PS_DONE 0x30
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#endif
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#define R600_INDIRECT_PARAMETERS_DELAY_EG 9
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#define R600_INDIRECT_PARAMETERS_WAIT_PIPELINE_CS 16
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#define R600_INDIRECT_PARAMETERS_COND_CS 13
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#define R600_INDIRECT_PARAMETERS_DELAY_CS \
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(2 * (r600_indirect_parameters_delay[rctx->b.family - CHIP_CEDAR] ? \
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r600_indirect_parameters_delay[rctx->b.family - CHIP_CEDAR] : \
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R600_INDIRECT_PARAMETERS_DELAY_EG))
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#define R600_INDIRECT_PARAMETERS_END_CS 9
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#define R600_INDIRECT_PARAMETERS_CS \
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(R600_INDIRECT_PARAMETERS_WAIT_PIPELINE_CS + \
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R600_INDIRECT_PARAMETERS_COND_CS + \
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R600_INDIRECT_PARAMETERS_DELAY_CS + \
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R600_INDIRECT_PARAMETERS_END_CS)
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struct r600_indirect_parameters {
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bool enabled;
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uint32_t counter;
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struct pipe_resource *internal;
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unsigned internal_offset;
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};
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struct r600_indirect_gpu_internal {
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uint32_t condition;
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uint32_t pad0;
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uint32_t fence;
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uint32_t pad1;
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};
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static const uint8_t r600_indirect_parameters_delay[CHIP_TAHITI - CHIP_CEDAR] = {
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[CHIP_REDWOOD - CHIP_CEDAR] = 3,
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[CHIP_JUNIPER - CHIP_CEDAR] = 3,
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[CHIP_CYPRESS - CHIP_CEDAR] = 3,
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[CHIP_PALM - CHIP_CEDAR] = 9,
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[CHIP_BARTS - CHIP_CEDAR] = 3,
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[CHIP_CAYMAN - CHIP_CEDAR] = 2,
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};
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static inline bool
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r600_is_indirect_parameters(const struct r600_indirect_parameters *const indirect_parameters)
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{
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return indirect_parameters->enabled;
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}
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static inline int
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r600_find_atomic_index(const struct r600_context *const rctx,
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const struct pipe_resource *const buffer)
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{
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int i;
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for (i = 0; i < EG_MAX_ATOMIC_BUFFERS; i++) {
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if (rctx->atomic_buffer_state.buffer[i].buffer == buffer)
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return i;
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}
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return -1;
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}
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static inline void
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r600_indirect_parameters_init(struct r600_context *rctx,
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struct radeon_cmdbuf *cs,
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const struct pipe_draw_indirect_info *indirect,
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struct r600_indirect_parameters *indirect_parameters,
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unsigned *cs_space)
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{
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if (unlikely(indirect && indirect->indirect_draw_count)) {
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uint64_t va_condition, va_fence;
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unsigned reloc_internal;
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void *ptr;
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assert(rctx->b.gfx_level >= EVERGREEN);
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assert(r600_find_atomic_index(rctx, indirect->indirect_draw_count) < 0);
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indirect_parameters->enabled = true;
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indirect_parameters->counter = 0;
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indirect_parameters->internal = NULL;
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u_upload_alloc(rctx->b.b.stream_uploader, 0,
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sizeof(struct r600_indirect_gpu_internal),
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256,
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&indirect_parameters->internal_offset,
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&indirect_parameters->internal, &ptr);
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if (unlikely(!ptr)) {
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indirect_parameters->enabled = false;
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return;
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}
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reloc_internal = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
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r600_resource(indirect_parameters->internal),
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RADEON_USAGE_READWRITE |
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RADEON_PRIO_SHADER_RW_BUFFER);
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va_fence = r600_resource(indirect_parameters->internal)->gpu_address +
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indirect_parameters->internal_offset +
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offsetof(struct r600_indirect_gpu_internal, fence);
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assert((va_fence - offsetof(struct r600_indirect_gpu_internal, fence)) % 16 == 0);
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/* fence = 0 */
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radeon_emit(cs, PKT3(PKT3_MEM_WRITE, 3, 0));
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radeon_emit(cs, va_fence);
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radeon_emit(cs, ((va_fence >> 32) & 0xff) | MEM_WRITE_32_BITS);
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radeon_emit(cs, 0);
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radeon_emit(cs, 0);
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radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
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radeon_emit(cs, reloc_internal);
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va_condition = r600_resource(indirect_parameters->internal)->gpu_address +
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indirect_parameters->internal_offset +
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offsetof(struct r600_indirect_gpu_internal, condition);
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assert((va_condition - offsetof(struct r600_indirect_gpu_internal, condition)) % 16 == 0);
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/* condition = 1 */
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radeon_emit(cs, PKT3(PKT3_MEM_WRITE, 3, 0));
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radeon_emit(cs, va_condition);
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radeon_emit(cs, ((va_condition >> 32) & 0xff) | MEM_WRITE_32_BITS);
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radeon_emit(cs, 1);
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radeon_emit(cs, 0);
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radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
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radeon_emit(cs, reloc_internal);
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*cs_space += (R600_INDIRECT_PARAMETERS_CS -
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R600_DRAW_PARAMETERS_DRAW_INDIRECT_CS) *
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indirect->draw_count;
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} else {
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indirect_parameters->enabled = false;
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}
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}
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static inline void
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r600_indirect_parameters_draw(struct r600_context *rctx,
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struct radeon_cmdbuf *cs,
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const struct pipe_draw_indirect_info *indirect,
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const unsigned index_size,
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const bool render_cond_bit,
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const unsigned multi_draw_offset,
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struct r600_indirect_parameters *indirect_parameters)
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{
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uint64_t va_draw_count, va_condition, va_fence;
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unsigned reloc_draw_count, reloc_internal;
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const unsigned wait_loop = r600_indirect_parameters_delay[rctx->b.family - CHIP_CEDAR] ?
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r600_indirect_parameters_delay[rctx->b.family - CHIP_CEDAR] :
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R600_INDIRECT_PARAMETERS_DELAY_EG;
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assert(radeon_check_cs(rctx, cs) || true);
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va_draw_count = r600_resource(indirect->indirect_draw_count)->gpu_address +
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indirect->indirect_draw_count_offset;
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va_condition = r600_resource(indirect_parameters->internal)->gpu_address +
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indirect_parameters->internal_offset +
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offsetof(struct r600_indirect_gpu_internal, condition);
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va_fence = r600_resource(indirect_parameters->internal)->gpu_address +
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indirect_parameters->internal_offset +
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offsetof(struct r600_indirect_gpu_internal, fence);
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reloc_draw_count = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
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r600_resource(indirect->indirect_draw_count),
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RADEON_USAGE_READWRITE |
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RADEON_PRIO_SHADER_RW_BUFFER);
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reloc_internal = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
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r600_resource(indirect_parameters->internal),
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RADEON_USAGE_READWRITE |
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RADEON_PRIO_SHADER_RW_BUFFER);
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assert((va_draw_count - indirect->indirect_draw_count_offset) % 16 == 0);
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assert((va_condition - offsetof(struct r600_indirect_gpu_internal, condition)) % 16 == 0);
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/* Wait until the graphic pipeline is empty */
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{
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radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOS, 3, 0));
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radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_PS_DONE) |
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EVENT_INDEX(6));
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radeon_emit(cs, va_fence);
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radeon_emit(cs, (2 << 29) |
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((va_fence >> 32) & 0xff));
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radeon_emit(cs, indirect_parameters->counter ^
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0x42f9dab5);
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radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
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radeon_emit(cs, reloc_internal);
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}
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{
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radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
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radeon_emit(cs, WAIT_REG_MEM_EQUAL |
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WAIT_REG_MEM_MEMORY |
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(0 << 8));
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radeon_emit(cs, va_fence);
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radeon_emit(cs, (va_fence >> 32) & 0xff);
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radeon_emit(cs, indirect_parameters->counter ^
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0x42f9dab5);
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radeon_emit(cs, ~0);
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radeon_emit(cs, 0xa);
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radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
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radeon_emit(cs, reloc_internal);
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}
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assert(radeon_check_cs(rctx, cs) == R600_INDIRECT_PARAMETERS_WAIT_PIPELINE_CS);
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/* condition = draw_count <= counter ? 0 : 1;
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* poll=memory write=memory
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* draw_count (2=less than or equal) counter */
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{
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radeon_emit(cs, PKT3(PKT3_COND_WRITE, 7, 0));
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radeon_emit(cs, (1<<8) | (1<<4) | 2);
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radeon_emit(cs, va_draw_count);
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radeon_emit(cs, (va_draw_count >> 32) & 0xff);
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radeon_emit(cs, indirect_parameters->counter);
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radeon_emit(cs, ~0);
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radeon_emit(cs, va_condition);
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radeon_emit(cs, (va_condition >> 32) & 0xff);
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radeon_emit(cs, 0);
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radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
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radeon_emit(cs, reloc_draw_count);
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radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
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radeon_emit(cs, reloc_internal);
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}
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assert(radeon_check_cs(rctx, cs) == R600_INDIRECT_PARAMETERS_COND_CS);
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/* The PKT3_COND_WRITE result is not available immediately.
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* Nine PKT3_PFP_SYNC_ME packets are sufficient to get the proper
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* delay on palm. We could also proceed with PKT3_NOP, but it
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* needs a loop of 192 packets. This loop count could be
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* calibrated with the piglit tf-count-arrays test.
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*
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* Three packets are sufficient on cypress and barts. The
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* value of nine should work on the remaining gpus. */
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for (int k = 0; k < wait_loop; k++) {
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radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
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radeon_emit(cs, 0);
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}
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assert(radeon_check_cs(rctx, cs) == R600_INDIRECT_PARAMETERS_DELAY_CS);
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/* Skip the next 5 dwords when the previous condition is false
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* PKT3_NOP: 2 dwords + EG_PKT3_DRAW_INDEX_INDIRECT or
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* EG_PKT3_DRAW_INDIRECT: 3 dwords */
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{
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radeon_emit(cs, PKT3(PKT3_COND_EXEC, 2, 0));
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radeon_emit(cs, va_condition);
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radeon_emit(cs, (va_condition >> 32) & 0xff);
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radeon_emit(cs, 5);
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radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
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radeon_emit(cs, reloc_internal);
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}
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if (index_size) {
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radeon_emit(cs, PKT3(EG_PKT3_DRAW_INDEX_INDIRECT, 1, render_cond_bit));
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radeon_emit(cs, indirect->offset + multi_draw_offset);
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radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
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} else {
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radeon_emit(cs, PKT3(EG_PKT3_DRAW_INDIRECT, 1, render_cond_bit));
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radeon_emit(cs, indirect->offset + multi_draw_offset);
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radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX);
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}
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assert(radeon_check_cs(rctx, cs) == R600_INDIRECT_PARAMETERS_END_CS);
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++indirect_parameters->counter;
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}
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static inline void
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r600_indirect_parameters_close(struct r600_context *rctx,
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const struct pipe_draw_indirect_info *indirect,
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struct r600_indirect_parameters *indirect_parameters)
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{
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if (unlikely(indirect_parameters->enabled)) {
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pipe_resource_reference(&indirect_parameters->internal, NULL);
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}
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}
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static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info,
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unsigned drawid_offset,
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const struct pipe_draw_indirect_info *indirect,
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@ -2241,6 +2530,7 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info
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const uint8_t *indirect_ptr = NULL;
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unsigned multi_draw_loop = 1;
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unsigned multi_draw_offset = 0;
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struct r600_indirect_parameters indirect_parameters;
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if (indirect && indirect->count_from_stream_output) {
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count_from_so = indirect->count_from_stream_output;
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@ -2409,6 +2699,13 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info
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&indirect_ptr,
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&num_patches,
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&cs_space);
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r600_indirect_parameters_init(rctx,
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cs,
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indirect,
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&indirect_parameters,
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&cs_space);
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} else {
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indirect_parameters.enabled = false;
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}
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/* Emit states. */
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@ -2569,9 +2866,21 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info
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radeon_emit(cs, PKT3(EG_PKT3_INDEX_BUFFER_SIZE, 0, 0));
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radeon_emit(cs, max_size);
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radeon_emit(cs, PKT3(EG_PKT3_DRAW_INDEX_INDIRECT, 1, render_cond_bit));
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radeon_emit(cs, indirect->offset);
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radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
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if (likely(!r600_is_indirect_parameters(&indirect_parameters))) {
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radeon_emit(cs, PKT3(EG_PKT3_DRAW_INDEX_INDIRECT, 1, render_cond_bit));
|
||||
radeon_emit(cs, indirect->offset);
|
||||
radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
|
||||
} else {
|
||||
assert(radeon_check_cs(rctx, cs) || true);
|
||||
|
||||
r600_indirect_parameters_draw(rctx,
|
||||
cs,
|
||||
indirect,
|
||||
index_size,
|
||||
render_cond_bit,
|
||||
multi_draw_offset,
|
||||
&indirect_parameters);
|
||||
}
|
||||
}
|
||||
}
|
||||
} else {
|
||||
|
|
@ -2597,13 +2906,27 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info
|
|||
if (likely(!indirect)) {
|
||||
radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
|
||||
radeon_emit(cs, draws[0].count);
|
||||
radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
|
||||
(count_from_so ? S_0287F0_USE_OPAQUE(1) : 0));
|
||||
}
|
||||
else {
|
||||
radeon_emit(cs, PKT3(EG_PKT3_DRAW_INDIRECT, 1, render_cond_bit));
|
||||
radeon_emit(cs, indirect->offset);
|
||||
if (likely(!r600_is_indirect_parameters(&indirect_parameters))) {
|
||||
radeon_emit(cs, PKT3(EG_PKT3_DRAW_INDIRECT, 1, render_cond_bit));
|
||||
radeon_emit(cs, indirect->offset);
|
||||
radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
|
||||
(count_from_so ? S_0287F0_USE_OPAQUE(1) : 0));
|
||||
} else {
|
||||
assert(radeon_check_cs(rctx, cs) || true);
|
||||
|
||||
r600_indirect_parameters_draw(rctx,
|
||||
cs,
|
||||
indirect,
|
||||
index_size,
|
||||
render_cond_bit,
|
||||
multi_draw_offset,
|
||||
&indirect_parameters);
|
||||
}
|
||||
}
|
||||
radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
|
||||
(count_from_so ? S_0287F0_USE_OPAQUE(1) : 0));
|
||||
}
|
||||
|
||||
/* SMX returns CONTEXT_DONE too early workaround */
|
||||
|
|
@ -2646,16 +2969,29 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info
|
|||
|
||||
assert(radeon_check_cs(rctx, cs) <= R600_DRAW_PARAMETERS_ENABLED_CS);
|
||||
|
||||
r600_draw_indirect(rctx,
|
||||
cs,
|
||||
indirect,
|
||||
index_size,
|
||||
render_cond_bit,
|
||||
multi_draw_offset);
|
||||
if (likely(!r600_is_indirect_parameters(&indirect_parameters)))
|
||||
r600_draw_indirect(rctx,
|
||||
cs,
|
||||
indirect,
|
||||
index_size,
|
||||
render_cond_bit,
|
||||
multi_draw_offset);
|
||||
else
|
||||
r600_indirect_parameters_draw(rctx,
|
||||
cs,
|
||||
indirect,
|
||||
index_size,
|
||||
render_cond_bit,
|
||||
multi_draw_offset,
|
||||
&indirect_parameters);
|
||||
}
|
||||
|
||||
if (rctx->b.gfx_level >= EVERGREEN)
|
||||
if (rctx->b.gfx_level >= EVERGREEN) {
|
||||
evergreen_emit_atomic_buffer_save(rctx, false, combined_atomics, global_atomic_count);
|
||||
r600_indirect_parameters_close(rctx,
|
||||
indirect,
|
||||
&indirect_parameters);
|
||||
}
|
||||
|
||||
if (rctx->trace_buf)
|
||||
eg_trace_emit(rctx);
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue