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brw: Run validation as soon as we have the CFG around

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Fixes: affa7567c2 ("intel/brw: Add phases to backend")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37148>
(cherry picked from commit 4e253184de)
This commit is contained in:
Caio Oliveira 2025-09-02 11:28:43 -07:00 • committed by Eric Engestrom
parent 4d60b13dee
commit f88d6cf795
2 changed files with 4 additions and 5 deletions
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2
.pick_status.json
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@ -9864,7 +9864,7 @@
"description": "brw: Run validation as soon as we have the CFG around",
"nominated": true,
"nomination_type": 2,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": "affa7567c291b9125afbd062ab77ed82d33330b6",
"notes": null

7
src/intel/compiler/brw_validate.cpp
View file

@ -291,12 +291,11 @@ brw_validate(const brw_shader &s)
{
const intel_device_info *devinfo = s.devinfo;
if (s.cfg)
s.cfg->validate(_mesa_shader_stage_to_abbrev(s.stage));
if (s.phase <= BRW_SHADER_PHASE_AFTER_NIR)
if (!s.cfg)
return;
s.cfg->validate(_mesa_shader_stage_to_abbrev(s.stage));
foreach_block(block, s.cfg) {
/* Track the last used address register. Usage of the address register
* in the IR should be limited to within a block, otherwise we would