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Author SHA1 Message Date
Rob Clark
fa5be473b8 ir3: Add disasm test macro for gen8 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:12:03 +00:00
Rob Clark
189e494249 ir3: Add (sy) before end of preamble when necessary 
We need to ensure GPR writes completes before the end of the preamble
to avoid writes landing after another preamble has already started.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:12:02 +00:00
Rob Clark
a48e4b8340 ir3: Extract out helper for nop flags 
Extract out a helper to add a flag to a nop, potentially re-using a
previous nop where possible.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:12:01 +00:00
Rob Clark
d1df3b4e39 ir3: Limit CS lock/unlock quirk 
We don't need this universally for everything >= gen7.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:12:01 +00:00
Rob Clark
e00bff2513 ir3: Fix cat3 latency 
The rule about only needing two cycles for 3rd src of cat3 instructions
only applies to variants of mad.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:12:01 +00:00
Rob Clark
02a4cc622d ir3: Fix gen8 instruction timings 
non_alu is still 6.  But AFAICT none of this changes since a7xx so these
were probably wrong on a7xx as well.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:12:01 +00:00
Rob Clark
3e7f200e1f ir3: Skip non-bindless ldc warmups 
Non bindless UBOs are pushed in cmdstream, so warmup instructions should
be unnecessary.  And cause hangs on gen8.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:12:01 +00:00
Rob Clark
d3e479b5c5 freedreno/registers: Fix gen8 swizzle enum 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:12:00 +00:00
Rob Clark
39bf9c0222 freedreno/registers: pm4 updates for gen8 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:12:00 +00:00
Rob Clark
fa45a48843 freedreno: Add gen8 chip template-fu 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:12:00 +00:00
Rob Clark
d786b6ad3e freedreno/drm-shim: Add a830 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:59 +00:00
Rob Clark
49c2271f26 freedreno/common: Add placeholder a8xx device 
Enough to have a gpu-id so that cffdump, disasm tests, etc, function.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:59 +00:00
Rob Clark
aa112be635 freedreno/common: Make max tile dimensions a param 
This value may differ between SKUs within a given generation.  So make
them parameters.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:59 +00:00
Rob Clark
96d6755e1f freedreno: Add gen8 device info 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:58 +00:00
Rob Clark
cb4a1134a9 freedreno/event: Extend event helpers for gen8 
There are some new events, but existing ones look the same.  So I think,
at least for now, we can keep the same table for gen7 and gen8.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:58 +00:00
Rob Clark
f35867686d freedreno/lrz: Extend lrz fc helpers for gen8 
The FC RAM is the same size as gen7.  Tbd if the metadata is also the
same.  So far we aren't enabling LRZ on gen8 yet, but need to do
something to make the compiler happy, so treat gen8 as it was the same
as gen7.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:58 +00:00
Rob Clark
ce4373ede5 freedreno/registers: Extend ncrb builder for new gens 
We want to use the A7XX version for anything CHIP>=A7XX.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:58 +00:00
Rob Clark
b5d307ef03 freedreno: Add chip range template helpers 
The c++ syntax for this isn't pretty.  But it is something we need in a
few places, so add some macros to hopefully make things easier on the
eyes.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:58 +00:00
Rob Clark
bcf4c8893c freedreno/registers: Fix GRAS_LRZ_CNTL definition 
Two fields moved to GRAS_LRZ_CNTL2 on a7xx+.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:57 +00:00
Rob Clark
f47c3d554b freedreno/registers: Name HYSTERESIS regs 
It looks like we'll need to program them for gen8.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:57 +00:00
Rob Clark
843ec5dbe7 freedreno/registers: Name RB_LRZ_CNTL2 
We'll need this for LRZ flush sequence on gen8

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:56 +00:00
Rob Clark
5c1bcaca24 freedreno/registers: Rename SP_HLSQ_MODE_CNTL 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:55 +00:00
Rob Clark
30a0ac7c0f freedreno/registers: Fix a few field names 
Give proper names to a few bitfields that we were already using.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:54 +00:00
Rob Clark
ccdd5eb49d freedreno/decode: Add extra indent levels 
Now we start hitting an extra indent level.

Fixes: d7db333b0e ("freedreno/decode: Add gen8 support")
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:53 +00:00
Rob Clark
e7a01c9c23 freedreno/decode: Print mode for compute shaders 
Similar to draw packets, it is useful to be able to see the mode and
pipe.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:53 +00:00
Rob Clark
c026a8f105 freedreno/decode: Fix bindless descriptor dumping 
We shouldn't be trying to calculate an offset from the bindless base reg
we looked up, as it already contains the array index.

We could lookup the index 0 reg offset, and calculate an offset from
there, but that breaks when the registers are not consecutive.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:52 +00:00
Rob Clark
f64e4a6d3e freedreno/a6xx: Fix debug comment 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:52 +00:00
Rob Clark
8480f32cfa freedreno/a6xx: Add helpers for preamble const loads 
Consolidate the logic about which path to take in one place.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:51 +00:00
Rob Clark
bafcdbf375 freedreno/a6xx: Add helper to set render mode 
Make it less awkward to deal with gen6/7 vs gen8 differences.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:51 +00:00
Rob Clark
b1218926bc freedreno/a6xx: Actually use lrz fast clear 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:50 +00:00
Rob Clark
d30a14b726 freedreno/a6xx: Be more precise about CP_SET_MARKER 
Set the mode before we start emitting registers.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:50 +00:00
Rob Clark
e0b6f97b9c freedreno/a6xx: Split preamble for gmem vs sysmem 
Possibly overkill currently, if we only preempt on bin boundaries.  But
might as well be complete in case that ever changes on the kernel side.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:49 +00:00
Rob Clark
701eb1ce8d freedreno/a6xx: Emit RB buffer setup for sysmem too 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:49 +00:00
Rob Clark
4ca78a296f freedreno/a6xx: Rework where we emit ccu cache cntl 
We don't need to re-emit it each tile.  But we do need to setup the
preemption to restore us to GMEM mode in case we get preempted on a tile
boundary.

While we are at it, rename the function to something more sensible.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:48 +00:00
Rob Clark
2439606518 freedreno/a6xx: Drop fd6_emit_blit() 
Now that we've corrected the event name (ie. CCU_RESOLVE to trigger the
resolve/unresolve engine) the helper name made less sense.  And it
doesn't really add any value.  So drop it.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:48 +00:00
Rob Clark
d7850b26b6 freedreno/a6xx: Drop emit_marker6() 
For a6xx+ devcoredump+crashdec does a good job in finding the CP
position on a crash.  I don't really use the scratch regs for this
purpose anymore.  So lets just drop this.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:47 +00:00
Rob Clark
791cb33da5 freedreno/a6xx: Pass cs to fd6_clear_lrz() 
Make it more obvious that all the clears go in the prologue.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:47 +00:00
Rob Clark
1a22daa157 freedreno: More ergonomic cs casting 
Make it less awkward to bridge back to legacy cmdstream builder.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:46 +00:00
Rob Clark
a24f3efd98 freedreno/a6xx: Add RB_DBG_ECO_MODE helper 
Avoid sprinkling the logic for blit vs non-blit values everywhere.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:46 +00:00
Rob Clark
56015d8cd9 freedreno/decode: Drop summary override for CRB 
It is just normal reg writes, we shouldn't handle it specially or
surpress summary state if enabled.  In summary mode we shouldn't print
each individual register write, but just show the values at draw/etc
time.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:45 +00:00
Rob Clark
b8fd1e2f7c freedreno/a6xx: genx helper for additional template param 
In a few cases we have a 2nd template param.  Add a helper for this so
adding new gens is less awkward.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:44 +00:00
Rob Clark
fb6dccc64c freedreno: flip template param order 
Prep for next patch.  We need the per-gen CHIP template param to be
last.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:44 +00:00
Rob Clark
b2349354e3 freedreno/a6xx: Use with_crb() helper 
Small cleanup that was missed when introducing the helper.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:44 +00:00
Rob Clark
392293ce48 freedreno/a6xx: Move VFD_RENDER_MODE emit 
The other two regs with RENDER_MODE fields are already part of
set_bin_size().

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:43 +00:00
Rob Clark
9e0942d4d9 freedreno/registers: Move FLAGS_REGID 
This field is only in SP_GS_OUTPUT_CNTL, and not the other regs that
re-use the same bitset.  So move it there.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:43 +00:00
Rob Clark
6233b5d841 freedreno/registers: Event cleanups 
Cleanup variants ranges, and in a couple cases rename events to match
docs.  In some cases events are marked valid thru A5XX, simply to
indicate that they were removed at some unknown point before A6XX.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:42 +00:00
Rob Clark
eeaf438911 freedreno/registers: Convert events to hex 
To match internal docs.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:40 +00:00
Rob Clark
74e77ce6a4 freedreno/crashdec: Log IBs to snapshot 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:39 +00:00
Rob Clark
8c372e8617 freedreno/crashdec: Dump cmdstream at end 
With gen8 we need to decode more sections before we have enough CP reg
vals to decode cmdstream.  So simplify things by just moving it to the
end.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:39 +00:00
Danylo Piliaiev
40b21f115d tu: Add custom resolve tracepoints
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Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38451>
 2025-12-08 20:44:47 +00:00