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freedreno/registers: Move FLAGS_REGID

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This field is only in SP_GS_OUTPUT_CNTL, and not the other regs that
re-use the same bitset.  So move it there.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
This commit is contained in:
Rob Clark 2025-10-19 08:52:33 -07:00 • committed by Marge Bot
parent 6233b5d841
commit 9e0942d4d9
7 changed files with 35 additions and 34 deletions
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7
src/freedreno/registers/adreno/a6xx.xml
View file

@ -3526,8 +3526,6 @@ by a particular renderpass/blit.
<bitset name="a6xx_sp_xs_output_cntl" inline="yes">
<!-- # of VS outputs including pos/psize -->
<bitfield name="OUT" low="0" high="5" type="uint"/>
<!-- FLAGS_REGID only for GS -->
<bitfield name="FLAGS_REGID" low="6" high="13" type="a3xx_regid"/>
</bitset>
<reg32 offset="0xa800" name="SP_VS_CNTL_0" type="a6xx_sp_xs_cntl_0" usage="rp_blit">
@ -3750,7 +3748,10 @@ by a particular renderpass/blit.
<reg32 offset="0xa872" name="SP_GS_BOOLEAN_CF_MASK" type="hex" usage="rp_blit"/>
<!-- TODO: exact same layout as 0xa802-0xa81a -->
<reg32 offset="0xa873" name="SP_GS_OUTPUT_CNTL" type="a6xx_sp_xs_output_cntl" usage="rp_blit"/>
<reg32 offset="0xa873" name="SP_GS_OUTPUT_CNTL" type="a6xx_sp_xs_output_cntl" usage="rp_blit">
<!-- FLAGS_REGID only for GS -->
<bitfield name="FLAGS_REGID" low="6" high="13" type="a3xx_regid"/>
</reg32>
<array offset="0xa874" name="SP_GS_OUTPUT" stride="1" length="16" usage="rp_blit">
<reg32 offset="0x0" name="REG">
<bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>

12
src/freedreno/tests/reference/crash.log
View file

@ -6672,7 +6672,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
- context: 0
00000000 SP_VS_CNTL_0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 }
00000000 SP_VS_BOOLEAN_CF_MASK: 0
00000000 SP_VS_OUTPUT_CNTL: { OUT = 0 | FLAGS_REGID = r0.x }
00000000 SP_VS_OUTPUT_CNTL: { OUT = 0 }
00000000 SP_VS_OUTPUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 }
00000000 SP_VS_OUTPUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 }
00000000 SP_VS_OUTPUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 }
@ -6718,7 +6718,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
00000000 SP_HS_INSTR_SIZE: 0
00000000 SP_DS_CNTL_0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 }
00000000 SP_DS_BOOLEAN_CF_MASK: 0
00000000 SP_DS_OUTPUT_CNTL: { OUT = 0 | FLAGS_REGID = r0.x }
00000000 SP_DS_OUTPUT_CNTL: { OUT = 0 }
00000000 SP_DS_OUTPUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 }
00000000 SP_DS_OUTPUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 }
00000000 SP_DS_OUTPUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 }
@ -6754,7 +6754,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
00000000 SP_GS_CNTL_0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 }
00000000 SP_GS_CNTL_1: 0
00000000 SP_GS_BOOLEAN_CF_MASK: 0
00000000 SP_GS_OUTPUT_CNTL: { OUT = 0 | FLAGS_REGID = r0.x }
00000000 SP_GS_OUTPUT_CNTL: { FLAGS_REGID = r0.x | OUT = 0 }
00000000 SP_GS_OUTPUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 }
00000000 SP_GS_OUTPUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 }
00000000 SP_GS_OUTPUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 }
@ -6802,7 +6802,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
- context: 1
00000000 SP_VS_CNTL_0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 }
00000000 SP_VS_BOOLEAN_CF_MASK: 0
00000000 SP_VS_OUTPUT_CNTL: { OUT = 0 | FLAGS_REGID = r0.x }
00000000 SP_VS_OUTPUT_CNTL: { OUT = 0 }
00000000 SP_VS_OUTPUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 }
00000000 SP_VS_OUTPUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 }
00000000 SP_VS_OUTPUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 }
@ -6848,7 +6848,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
00000000 SP_HS_INSTR_SIZE: 0
00000000 SP_DS_CNTL_0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 }
00000000 SP_DS_BOOLEAN_CF_MASK: 0
00000000 SP_DS_OUTPUT_CNTL: { OUT = 0 | FLAGS_REGID = r0.x }
00000000 SP_DS_OUTPUT_CNTL: { OUT = 0 }
00000000 SP_DS_OUTPUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 }
00000000 SP_DS_OUTPUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 }
00000000 SP_DS_OUTPUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 }
@ -6884,7 +6884,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
00000000 SP_GS_CNTL_0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 }
00000000 SP_GS_CNTL_1: 0
00000000 SP_GS_BOOLEAN_CF_MASK: 0
00000000 SP_GS_OUTPUT_CNTL: { OUT = 0 | FLAGS_REGID = r0.x }
00000000 SP_GS_OUTPUT_CNTL: { FLAGS_REGID = r0.x | OUT = 0 }
00000000 SP_GS_OUTPUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 }
00000000 SP_GS_OUTPUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 }
00000000 SP_GS_OUTPUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 }

20
src/freedreno/tests/reference/crash_prefetch.log
View file

@ -7279,7 +7279,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
- context: 0
00100080 SP_VS_CNTL_0: { MERGEDREGS | THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | BRANCHSTACK = 0 }
00000000 SP_VS_BOOLEAN_CF_MASK: 0
00000001 SP_VS_OUTPUT_CNTL: { OUT = 1 | FLAGS_REGID = r0.x }
00000001 SP_VS_OUTPUT_CNTL: { OUT = 1 }
00000f00 SP_VS_OUTPUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 }
00000000 SP_VS_OUTPUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 }
00000000 SP_VS_OUTPUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 }
@ -7325,7 +7325,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
00000000 SP_HS_INSTR_SIZE: 0
00000000 SP_DS_CNTL_0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 }
00000000 SP_DS_BOOLEAN_CF_MASK: 0
00000000 SP_DS_OUTPUT_CNTL: { OUT = 0 | FLAGS_REGID = r0.x }
00000000 SP_DS_OUTPUT_CNTL: { OUT = 0 }
00000000 SP_DS_OUTPUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 }
00000000 SP_DS_OUTPUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 }
00000000 SP_DS_OUTPUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 }
@ -7361,7 +7361,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
00000000 SP_GS_CNTL_0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 }
00000000 SP_GS_CNTL_1: 0
00000000 SP_GS_BOOLEAN_CF_MASK: 0
00000000 SP_GS_OUTPUT_CNTL: { OUT = 0 | FLAGS_REGID = r0.x }
00000000 SP_GS_OUTPUT_CNTL: { FLAGS_REGID = r0.x | OUT = 0 }
00000000 SP_GS_OUTPUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 }
00000000 SP_GS_OUTPUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 }
00000000 SP_GS_OUTPUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 }
@ -7409,7 +7409,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
- context: 1
00100080 SP_VS_CNTL_0: { MERGEDREGS | THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | BRANCHSTACK = 0 }
00000000 SP_VS_BOOLEAN_CF_MASK: 0
00000001 SP_VS_OUTPUT_CNTL: { OUT = 1 | FLAGS_REGID = r0.x }
00000001 SP_VS_OUTPUT_CNTL: { OUT = 1 }
00000f00 SP_VS_OUTPUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 }
00000000 SP_VS_OUTPUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 }
00000000 SP_VS_OUTPUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 }
@ -7455,7 +7455,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
00000000 SP_HS_INSTR_SIZE: 0
00000000 SP_DS_CNTL_0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 }
00000000 SP_DS_BOOLEAN_CF_MASK: 0
00000000 SP_DS_OUTPUT_CNTL: { OUT = 0 | FLAGS_REGID = r0.x }
00000000 SP_DS_OUTPUT_CNTL: { OUT = 0 }
00000000 SP_DS_OUTPUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 }
00000000 SP_DS_OUTPUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 }
00000000 SP_DS_OUTPUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 }
@ -7491,7 +7491,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
00000000 SP_GS_CNTL_0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 }
00000000 SP_GS_CNTL_1: 0
00000000 SP_GS_BOOLEAN_CF_MASK: 0
00000000 SP_GS_OUTPUT_CNTL: { OUT = 0 | FLAGS_REGID = r0.x }
00000000 SP_GS_OUTPUT_CNTL: { FLAGS_REGID = r0.x | OUT = 0 }
00000000 SP_GS_OUTPUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 }
00000000 SP_GS_OUTPUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 }
00000000 SP_GS_OUTPUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 }
@ -8851,7 +8851,7 @@ got cmdszdw=38
!+ 00000001 VFD_FETCH_INSTR[0].STEP_RATE: 1
!+ 00000003 VFD_DEST_CNTL[0].INSTR: { WRITEMASK = 0x3 | REGID = r0.x }
!+ 00100080 SP_VS_CNTL_0: { MERGEDREGS | THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | BRANCHSTACK = 0 }
!+ 00000001 SP_VS_OUTPUT_CNTL: { OUT = 1 | FLAGS_REGID = r0.x }
!+ 00000001 SP_VS_OUTPUT_CNTL: { OUT = 1 }
!+ 00000f00 SP_VS_OUTPUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 }
+ 00000000 SP_VS_VPC_DEST[0].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 }
+ 00000000 SP_VS_PROGRAM_COUNTER_OFFSET: 0
@ -9536,7 +9536,7 @@ got cmdszdw=38
+ 00000001 VFD_FETCH_INSTR[0].STEP_RATE: 1
+ 00000003 VFD_DEST_CNTL[0].INSTR: { WRITEMASK = 0x3 | REGID = r0.x }
+ 00100080 SP_VS_CNTL_0: { MERGEDREGS | THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | BRANCHSTACK = 0 }
+ 00000001 SP_VS_OUTPUT_CNTL: { OUT = 1 | FLAGS_REGID = r0.x }
+ 00000001 SP_VS_OUTPUT_CNTL: { OUT = 1 }
+ 00000f00 SP_VS_OUTPUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 }
+ 00000000 SP_VS_VPC_DEST[0].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 }
+ 00000000 SP_VS_PROGRAM_COUNTER_OFFSET: 0
@ -10231,7 +10231,7 @@ got cmdszdw=38
+ 00000001 VFD_FETCH_INSTR[0].STEP_RATE: 1
+ 00000003 VFD_DEST_CNTL[0].INSTR: { WRITEMASK = 0x3 | REGID = r0.x }
+ 00100080 SP_VS_CNTL_0: { MERGEDREGS | THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | BRANCHSTACK = 0 }
+ 00000001 SP_VS_OUTPUT_CNTL: { OUT = 1 | FLAGS_REGID = r0.x }
+ 00000001 SP_VS_OUTPUT_CNTL: { OUT = 1 }
+ 00000f00 SP_VS_OUTPUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 }
+ 00000000 SP_VS_VPC_DEST[0].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 }
+ 00000000 SP_VS_PROGRAM_COUNTER_OFFSET: 0
@ -10852,7 +10852,7 @@ ESTIMATED CRASH LOCATION!
+ 00000001 VFD_FETCH_INSTR[0].STEP_RATE: 1
+ 00000003 VFD_DEST_CNTL[0].INSTR: { WRITEMASK = 0x3 | REGID = r0.x }
+ 00100080 SP_VS_CNTL_0: { MERGEDREGS | THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | BRANCHSTACK = 0 }
+ 00000001 SP_VS_OUTPUT_CNTL: { OUT = 1 | FLAGS_REGID = r0.x }
+ 00000001 SP_VS_OUTPUT_CNTL: { OUT = 1 }
+ 00000f00 SP_VS_OUTPUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 }
+ 00000000 SP_VS_VPC_DEST[0].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 }
+ 00000000 SP_VS_PROGRAM_COUNTER_OFFSET: 0

4
src/freedreno/tests/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log
View file

@ -888,7 +888,7 @@ cmdstream[0]: 265 dwords
PC_VS_CNTL: { STRIDE_IN_VPC = 8 | CLIP_MASK = 0 }
00000000010542cc: 0000: 489b0101 00000008
write SP_VS_OUTPUT_CNTL (a802)
SP_VS_OUTPUT_CNTL: { OUT = 2 | FLAGS_REGID = r0.x }
SP_VS_OUTPUT_CNTL: { OUT = 2 }
00000000010542d4: 0000: 48a80201 00000002
write VPC_VS_SIV_CNTL (9104)
VPC_VS_SIV_CNTL: { LAYERLOC = 255 | VIEWLOC = 255 }
@ -1369,7 +1369,7 @@ cmdstream[0]: 265 dwords
!+ 0000004f VFD_DEST_CNTL[0x1].INSTR: { WRITEMASK = 0xf | REGID = r1.x }
!+ 00000081 VFD_DEST_CNTL[0x2].INSTR: { WRITEMASK = 0x1 | REGID = r2.x }
!+ 80100180 SP_VS_CNTL_0: { MERGEDREGS | THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 3 | BRANCHSTACK = 0 | 0x80000000 }
!+ 00000002 SP_VS_OUTPUT_CNTL: { OUT = 2 | FLAGS_REGID = r0.x }
!+ 00000002 SP_VS_OUTPUT_CNTL: { OUT = 2 }
!+ 0f000f08 SP_VS_OUTPUT[0].REG: { A_REGID = r2.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0xf }
!+ 00000400 SP_VS_VPC_DEST[0].REG: { OUTLOC0 = 0 | OUTLOC1 = 4 | OUTLOC2 = 0 | OUTLOC3 = 0 }
!+ 01054000 SP_VS_BASE: 0x1054000 base=1054000, offset=0, size=12288

8
src/freedreno/tests/reference/fd-clouds.log
View file

@ -651,7 +651,7 @@ cmdstream[0]: 1023 dwords
SP_HS_CNTL_1: 0
0000000001121078: 0000: 48a83101 00000000
write SP_VS_OUTPUT_CNTL (a802)
SP_VS_OUTPUT_CNTL: { OUT = 1 | FLAGS_REGID = r0.x }
SP_VS_OUTPUT_CNTL: { OUT = 1 }
0000000001121080: 0000: 48a80201 00000001
write VPC_PS_CNTL (9304)
VPC_PS_CNTL: { NUMNONPOSVAR = 0 | PRIMIDLOC = 255 | VIEWIDLOC = 255 }
@ -1047,7 +1047,7 @@ cmdstream[0]: 1023 dwords
!+ 0000000f VFD_DEST_CNTL[0].INSTR: { WRITEMASK = 0xf | REGID = r0.x }
!+ 00000001 VFD_POWER_CNTL: 0x1
!+ 80100080 SP_VS_CNTL_0: { MERGEDREGS | THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | BRANCHSTACK = 0 | 0x80000000 }
!+ 00000001 SP_VS_OUTPUT_CNTL: { OUT = 1 | FLAGS_REGID = r0.x }
!+ 00000001 SP_VS_OUTPUT_CNTL: { OUT = 1 }
!+ 00000f00 SP_VS_OUTPUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 }
+ 00000000 SP_VS_VPC_DEST[0].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 }
+ 00000000 SP_VS_PROGRAM_COUNTER_OFFSET: 0
@ -1867,7 +1867,7 @@ cmdstream[0]: 1023 dwords
SP_HS_CNTL_1: 0
0000000001120078: 0000: 48a83101 00000000
write SP_VS_OUTPUT_CNTL (a802)
SP_VS_OUTPUT_CNTL: { OUT = 1 | FLAGS_REGID = r0.x }
SP_VS_OUTPUT_CNTL: { OUT = 1 }
0000000001120080: 0000: 48a80201 00000001
write VPC_PS_CNTL (9304)
VPC_PS_CNTL: { NUMNONPOSVAR = 0 | PRIMIDLOC = 255 | VIEWIDLOC = 255 }
@ -5174,7 +5174,7 @@ cmdstream[0]: 1023 dwords
+ 00000001 VFD_FETCH_INSTR[0].STEP_RATE: 1
+ 0000000f VFD_DEST_CNTL[0].INSTR: { WRITEMASK = 0xf | REGID = r0.x }
+ 80100080 SP_VS_CNTL_0: { MERGEDREGS | THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 1 | BRANCHSTACK = 0 | 0x80000000 }
+ 00000001 SP_VS_OUTPUT_CNTL: { OUT = 1 | FLAGS_REGID = r0.x }
+ 00000001 SP_VS_OUTPUT_CNTL: { OUT = 1 }
+ 00000f00 SP_VS_OUTPUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 }
+ 00000000 SP_VS_VPC_DEST[0].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 }
!+ 01012000 SP_VS_BASE: 0x1012000 base=1012000, offset=0, size=128

14
src/freedreno/tests/reference/prefetch-test.log
View file

@ -7635,7 +7635,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
- context: 0
00108280 SP_VS_CNTL_0: { MERGEDREGS | THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 5 | BRANCHSTACK = 2 }
00000000 SP_VS_BOOLEAN_CF_MASK: 0
00000002 SP_VS_OUTPUT_CNTL: { OUT = 2 | FLAGS_REGID = r0.x }
00000002 SP_VS_OUTPUT_CNTL: { OUT = 2 }
0f0e0312 SP_VS_OUTPUT[0].REG: { A_REGID = r4.z | A_COMPMASK = 0x3 | B_REGID = r3.z | B_COMPMASK = 0xf }
00000000 SP_VS_OUTPUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 }
00000000 SP_VS_OUTPUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 }
@ -7681,7 +7681,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
00000000 SP_HS_INSTR_SIZE: 0
00000000 SP_DS_CNTL_0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 }
00000000 SP_DS_BOOLEAN_CF_MASK: 0
00000000 SP_DS_OUTPUT_CNTL: { OUT = 0 | FLAGS_REGID = r0.x }
00000000 SP_DS_OUTPUT_CNTL: { OUT = 0 }
00000000 SP_DS_OUTPUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 }
00000000 SP_DS_OUTPUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 }
00000000 SP_DS_OUTPUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 }
@ -7717,7 +7717,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
00000000 SP_GS_CNTL_0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 }
00000000 SP_GS_CNTL_1: 0
00000000 SP_GS_BOOLEAN_CF_MASK: 0
00000000 SP_GS_OUTPUT_CNTL: { OUT = 0 | FLAGS_REGID = r0.x }
00000000 SP_GS_OUTPUT_CNTL: { FLAGS_REGID = r0.x | OUT = 0 }
00000000 SP_GS_OUTPUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 }
00000000 SP_GS_OUTPUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 }
00000000 SP_GS_OUTPUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 }
@ -7765,7 +7765,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
- context: 1
00108280 SP_VS_CNTL_0: { MERGEDREGS | THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 5 | BRANCHSTACK = 2 }
00000000 SP_VS_BOOLEAN_CF_MASK: 0
00000002 SP_VS_OUTPUT_CNTL: { OUT = 2 | FLAGS_REGID = r0.x }
00000002 SP_VS_OUTPUT_CNTL: { OUT = 2 }
0f0e0312 SP_VS_OUTPUT[0].REG: { A_REGID = r4.z | A_COMPMASK = 0x3 | B_REGID = r3.z | B_COMPMASK = 0xf }
00000000 SP_VS_OUTPUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 }
00000000 SP_VS_OUTPUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 }
@ -7811,7 +7811,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
00000000 SP_HS_INSTR_SIZE: 0
00000000 SP_DS_CNTL_0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 }
00000000 SP_DS_BOOLEAN_CF_MASK: 0
00000000 SP_DS_OUTPUT_CNTL: { OUT = 0 | FLAGS_REGID = r0.x }
00000000 SP_DS_OUTPUT_CNTL: { OUT = 0 }
00000000 SP_DS_OUTPUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 }
00000000 SP_DS_OUTPUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 }
00000000 SP_DS_OUTPUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 }
@ -7847,7 +7847,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d)
00000000 SP_GS_CNTL_0: { THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 }
00000000 SP_GS_CNTL_1: 0
00000000 SP_GS_BOOLEAN_CF_MASK: 0
00000000 SP_GS_OUTPUT_CNTL: { OUT = 0 | FLAGS_REGID = r0.x }
00000000 SP_GS_OUTPUT_CNTL: { FLAGS_REGID = r0.x | OUT = 0 }
00000000 SP_GS_OUTPUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 }
00000000 SP_GS_OUTPUT[0x1].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 }
00000000 SP_GS_OUTPUT[0x2].REG: { A_REGID = r0.x | A_COMPMASK = 0 | B_REGID = r0.x | B_COMPMASK = 0 }
@ -8927,7 +8927,7 @@ got cmdszdw=416
!+ 00000001 VFD_FETCH_INSTR[0].STEP_RATE: 1
!+ 00000007 VFD_DEST_CNTL[0].INSTR: { WRITEMASK = 0x7 | REGID = r0.x }
!+ 00108280 SP_VS_CNTL_0: { MERGEDREGS | THREADMODE = MULTI | HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 5 | BRANCHSTACK = 2 }
!+ 00000002 SP_VS_OUTPUT_CNTL: { OUT = 2 | FLAGS_REGID = r0.x }
!+ 00000002 SP_VS_OUTPUT_CNTL: { OUT = 2 }
!+ 0f0e0312 SP_VS_OUTPUT[0].REG: { A_REGID = r4.z | A_COMPMASK = 0x3 | B_REGID = r3.z | B_COMPMASK = 0xf }
!+ 00000200 SP_VS_VPC_DEST[0].REG: { OUTLOC0 = 0 | OUTLOC1 = 2 | OUTLOC2 = 0 | OUTLOC3 = 0 }
+ 00000000 SP_VS_PROGRAM_COUNTER_OFFSET: 0

4
src/gallium/drivers/freedreno/a6xx/fd6_program.cc
View file

@ -861,7 +861,7 @@ emit_vpc(fd_crb &crb, const struct program_builder *b)
switch (last_shader->type) {
case MESA_SHADER_VERTEX:
crb.add(A6XX_SP_VS_OUTPUT_CNTL(.out = linkage.cnt, .flags_regid = flags_regid));
crb.add(A6XX_SP_VS_OUTPUT_CNTL(.out = linkage.cnt));
crb.add(VPC_VS_SIV_CNTL(CHIP,
.layerloc = layer_loc,
.viewloc = view_loc,
@ -880,7 +880,7 @@ emit_vpc(fd_crb &crb, const struct program_builder *b)
));
break;
case MESA_SHADER_TESS_EVAL:
crb.add(A6XX_SP_DS_OUTPUT_CNTL(.out = linkage.cnt, .flags_regid = flags_regid));
crb.add(A6XX_SP_DS_OUTPUT_CNTL(.out = linkage.cnt));
crb.add(VPC_DS_SIV_CNTL(CHIP,
.layerloc = layer_loc,
.viewloc = view_loc,