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freedreno/registers: Fix GRAS_LRZ_CNTL definition

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Two fields moved to GRAS_LRZ_CNTL2 on a7xx+.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
This commit is contained in:
Rob Clark 2025-11-03 12:42:42 -08:00 • committed by Marge Bot
parent f47c3d554b
commit bcf4c8893c
2 changed files with 6 additions and 4 deletions
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8
src/freedreno/registers/adreno/a6xx.xml
View file

@ -1927,7 +1927,6 @@ by a particular renderpass/blit.
- 0.0 if GREATER
- 1.0 if LESS
</doc>
<bitfield name="FC_ENABLE" pos="3" type="boolean" variants="A6XX"/>
<!-- set when depth-test + depth-write enabled -->
<bitfield name="Z_WRITE_ENABLE" pos="4" type="boolean"/>
<bitfield name="Z_BOUNDS_ENABLE" pos="5" type="boolean"/>
@ -1941,11 +1940,14 @@ by a particular renderpass/blit.
Disable LRZ based on previous direction and the current one.
If DIR_WRITE is not enabled - there is no write to direction buffer.
</doc>
<bitfield name="DISABLE_ON_WRONG_DIR" pos="9" type="boolean" variants="A6XX"/>
<bitfield name="Z_FUNC" low="11" high="13" type="adreno_compare_func" variants="A7XX-"/>
</bitset>
<reg32 offset="0x8100" name="GRAS_LRZ_CNTL" type="a6xx_gras_lrz_cntl" usage="rp_blit" variants="A6XX-A7XX"/>
<reg32 offset="0x8100" name="GRAS_LRZ_CNTL" type="a6xx_gras_lrz_cntl" usage="rp_blit" variants="A6XX">
<bitfield name="FC_ENABLE" pos="3" type="boolean" variants="A6XX"/>
<bitfield name="DISABLE_ON_WRONG_DIR" pos="9" type="boolean" variants="A6XX"/>
</reg32>
<reg32 offset="0x8100" name="GRAS_LRZ_CNTL" type="a6xx_gras_lrz_cntl" usage="rp_blit" variants="A7XX"/>
<reg32 offset="0x8212" name="GRAS_LRZ_CNTL" type="a6xx_gras_lrz_cntl" usage="rp_blit" variants="A8XX-"/>
<reg32 offset="0x8007" name="GRAS_LRZ_CB_CNTL" variants="A7XX" usage="rp_blit">

2
src/gallium/drivers/freedreno/a6xx/fd6_emit.cc
View file

@ -232,9 +232,9 @@ build_lrz(struct fd6_emit *emit) assert_dt
.enable = lrz.enable,
.lrz_write = lrz.write,
.greater = lrz.direction == FD_LRZ_GREATER,
.fc_enable = false, /* a6xx only */
.z_write_enable = lrz.test,
.z_bounds_enable = lrz.z_bounds_enable,
.fc_enable = false, /* a6xx only */
.disable_on_wrong_dir = false, /* a6xx only */
))
.add(A6XX_RB_LRZ_CNTL(.enable = lrz.enable, ))