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freedreno/registers: Convert events to hex
To match internal docs. Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
This commit is contained in:
Rob Clark
Marge Bot
parent
74e77ce6a4
commit
eeaf438911
1 changed files with 68 additions and 68 deletions
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@ -6,103 +6,103 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
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<import file="adreno/adreno_common.xml"/>
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<enum name="vgt_event_type" varset="chip">
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<value name="VS_DEALLOC" value="0"/>
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<value name="PS_DEALLOC" value="1" variants="A2XX-A6XX"/>
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<value name="VS_DONE_TS" value="2"/>
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<value name="PS_DONE_TS" value="3"/>
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<value name="VS_DEALLOC" value="0x00"/>
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<value name="PS_DEALLOC" value="0x01" variants="A2XX-A6XX"/>
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<value name="VS_DONE_TS" value="0x02"/>
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<value name="PS_DONE_TS" value="0x03"/>
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<doc>
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Flushes dirty data from UCHE, and also writes a GPU timestamp to
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the address if one is provided.
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</doc>
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<value name="CACHE_FLUSH_TS" value="4"/>
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<value name="CONTEXT_DONE" value="5"/>
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<value name="CACHE_FLUSH" value="6" variants="A2XX-A4XX"/>
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<value name="VIZQUERY_START" value="7" variants="A2XX"/>
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<value name="HLSQ_FLUSH" value="7" variants="A3XX-A4XX"/>
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<value name="VIZQUERY_END" value="8" variants="A2XX"/>
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<value name="SC_WAIT_WC" value="9" variants="A2XX"/>
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<value name="WRITE_PRIMITIVE_COUNTS" value="9" variants="A6XX-"/>
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<value name="START_PRIMITIVE_CTRS" value="11" variants="A6XX-"/>
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<value name="STOP_PRIMITIVE_CTRS" value="12" variants="A6XX-"/>
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<value name="CACHE_FLUSH_TS" value="0x04"/>
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<value name="CONTEXT_DONE" value="0x05"/>
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<value name="CACHE_FLUSH" value="0x06" variants="A2XX-A4XX"/>
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<value name="VIZQUERY_START" value="0x07" variants="A2XX"/>
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<value name="HLSQ_FLUSH" value="0x07" variants="A3XX-A4XX"/>
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<value name="VIZQUERY_END" value="0x08" variants="A2XX"/>
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<value name="SC_WAIT_WC" value="0x09" variants="A2XX"/>
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<value name="WRITE_PRIMITIVE_COUNTS" value="0x09" variants="A6XX-"/>
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<value name="START_PRIMITIVE_CTRS" value="0x0b" variants="A6XX-"/>
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<value name="STOP_PRIMITIVE_CTRS" value="0x0c" variants="A6XX-"/>
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<!-- Not sure that these 4 events don't have the same meaning as on A5XX+ -->
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<value name="RST_PIX_CNT" value="13" variants="A2XX-A4XX"/>
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<value name="RST_VTX_CNT" value="14" variants="A2XX-A4XX"/>
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<value name="TILE_FLUSH" value="15" variants="A2XX-A4XX"/>
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<value name="STAT_EVENT" value="16" variants="A2XX-A4XX"/>
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<value name="CACHE_FLUSH_AND_INV_TS_EVENT" value="20" variants="A2XX-A4XX"/>
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<value name="RST_PIX_CNT" value="0x0d" variants="A2XX-A4XX"/>
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<value name="RST_VTX_CNT" value="0x0e" variants="A2XX-A4XX"/>
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<value name="TILE_FLUSH" value="0x0f" variants="A2XX-A4XX"/>
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<value name="STAT_EVENT" value="0x10" variants="A2XX-A4XX"/>
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<value name="CACHE_FLUSH_AND_INV_TS_EVENT" value="0x14" variants="A2XX-A4XX"/>
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<doc>
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If A6XX_RB_SAMPLE_COUNTER_CNTL.copy is true, writes OQ Z passed
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sample counts to RB_SAMPLE_COUNTER_BASE. This writes to main
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memory, skipping UCHE.
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</doc>
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<value name="ZPASS_DONE" value="21"/>
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<value name="CACHE_FLUSH_AND_INV_EVENT" value="22" variants="A2XX"/>
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<value name="ZPASS_DONE" value="0x15"/>
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<value name="CACHE_FLUSH_AND_INV_EVENT" value="0x16" variants="A2XX"/>
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<doc>
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Writes the GPU timestamp to the address that follows, once RB
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access and flushes are complete.
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</doc>
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<value name="RB_DONE_TS" value="22" variants="A3XX-"/>
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<value name="RB_DONE_TS" value="0x16" variants="A3XX-"/>
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<value name="PERFCOUNTER_START" value="23" variants="A2XX-A4XX"/>
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<value name="PERFCOUNTER_STOP" value="24" variants="A2XX-A4XX"/>
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<value name="VS_FETCH_DONE" value="27"/>
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<value name="FACENESS_FLUSH" value="28" variants="A2XX-A4XX"/>
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<value name="PERFCOUNTER_START" value="0x17" variants="A2XX-A4XX"/>
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<value name="PERFCOUNTER_STOP" value="0x18" variants="A2XX-A4XX"/>
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<value name="VS_FETCH_DONE" value="0x1b"/>
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<value name="FACENESS_FLUSH" value="0x1c" variants="A2XX-A4XX"/>
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<!-- a5xx events -->
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<value name="WT_DONE_TS" value="8" variants="A5XX-"/>
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<value name="START_FRAGMENT_CTRS" value="13" variants="A5XX-"/>
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<value name="STOP_FRAGMENT_CTRS" value="14" variants="A5XX-"/>
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<value name="START_COMPUTE_CTRS" value="15" variants="A5XX-"/>
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<value name="STOP_COMPUTE_CTRS" value="16" variants="A5XX-"/>
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<value name="FLUSH_SO_0" value="17" variants="A5XX-"/>
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<value name="FLUSH_SO_1" value="18" variants="A5XX-"/>
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<value name="FLUSH_SO_2" value="19" variants="A5XX-"/>
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<value name="FLUSH_SO_3" value="20" variants="A5XX-"/>
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<value name="WT_DONE_TS" value="0x08" variants="A5XX-"/>
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<value name="START_FRAGMENT_CTRS" value="0x0d" variants="A5XX-"/>
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<value name="STOP_FRAGMENT_CTRS" value="0x0e" variants="A5XX-"/>
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<value name="START_COMPUTE_CTRS" value="0x0f" variants="A5XX-"/>
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<value name="STOP_COMPUTE_CTRS" value="0x10" variants="A5XX-"/>
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<value name="FLUSH_SO_0" value="0x11" variants="A5XX-"/>
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<value name="FLUSH_SO_1" value="0x12" variants="A5XX-"/>
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<value name="FLUSH_SO_2" value="0x13" variants="A5XX-"/>
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<value name="FLUSH_SO_3" value="0x14" variants="A5XX-"/>
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<doc>
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Invalidates depth attachment data from the CCU. We assume this
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happens in the last stage.
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</doc>
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<value name="PC_CCU_INVALIDATE_DEPTH" value="24" variants="A5XX-"/>
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<value name="PC_CCU_INVALIDATE_DEPTH" value="0x18" variants="A5XX-"/>
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<doc>
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Invalidates color attachment data from the CCU. We assume this
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happens in the last stage.
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</doc>
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<value name="PC_CCU_INVALIDATE_COLOR" value="25" variants="A5XX-"/>
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<value name="PC_CCU_INVALIDATE_COLOR" value="0x19" variants="A5XX-"/>
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<doc>
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Flushes the small cache used by CP_EVENT_WRITE::BLIT (which,
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along with its registers, would be better named RESOLVE).
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</doc>
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<value name="PC_CCU_RESOLVE_TS" value="26" variants="A6XX"/>
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<value name="PC_CCU_RESOLVE_TS" value="0x1a" variants="A6XX"/>
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<doc>
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Flushes depth attachment data from the CCU. We assume this
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happens in the last stage.
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</doc>
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<value name="PC_CCU_FLUSH_DEPTH_TS" value="28" variants="A5XX-"/>
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<value name="PC_CCU_FLUSH_DEPTH_TS" value="0x1c" variants="A5XX-"/>
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<doc>
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Flushes color attachment data from the CCU. We assume this
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happens in the last stage.
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</doc>
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<value name="PC_CCU_FLUSH_COLOR_TS" value="29" variants="A5XX-"/>
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<value name="PC_CCU_FLUSH_COLOR_TS" value="0x1d" variants="A5XX-"/>
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<doc>
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2D blit to resolve GMEM to system memory (skipping CCU) at the
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end of a render pass. Compare to CP_BLIT's BLIT_OP_SCALE for
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more general blitting.
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</doc>
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<value name="BLIT" value="30" variants="A5XX-"/>
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<value name="BLIT" value="0x1e" variants="A5XX-"/>
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<doc>
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Flip between the primary and secondary LRZ buffers. This is used
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for concurrent binning, so that BV can write to one buffer while
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BR reads from the other.
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</doc>
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<value name="LRZ_FLIP_BUFFER" value="36" variants="A7XX-"/>
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<value name="LRZ_FLIP_BUFFER" value="0x24" variants="A7XX-"/>
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<doc>
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Clears based on GRAS_LRZ_CNTL configuration, could clear
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@ -115,44 +115,44 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
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CUR_DIR_UNSET = 0x3
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Clear of direction means setting the direction to CUR_DIR_UNSET.
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</doc>
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<value name="LRZ_CLEAR" value="37" variants="A5XX-"/>
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<value name="LRZ_CLEAR" value="0x25" variants="A5XX-"/>
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<value name="LRZ_FLUSH" value="38" variants="A5XX-"/>
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<value name="BLIT_OP_FILL_2D" value="39" variants="A5XX-"/>
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<value name="BLIT_OP_COPY_2D" value="40" variants="A5XX-A6XX"/>
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<value name="LRZ_CACHE_INVALIDATE" value="40" variants="A7XX-"/>
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<value name="LRZ_Q_CACHE_INVALIDATE" value="41" variants="A7XX-"/>
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<value name="BLIT_OP_SCALE_2D" value="42" variants="A5XX-"/>
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<value name="CONTEXT_DONE_2D" value="43" variants="A5XX-"/>
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<value name="VSC_BINNING_START" value="44" variants="A5XX-"/>
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<value name="VSC_BINNING_END" value="45" variants="A5XX-"/>
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<value name="LRZ_FLUSH" value="0x26" variants="A5XX-"/>
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<value name="BLIT_OP_FILL_2D" value="0x27" variants="A5XX-"/>
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<value name="BLIT_OP_COPY_2D" value="0x28" variants="A5XX-A6XX"/>
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<value name="LRZ_CACHE_INVALIDATE" value="0x28" variants="A7XX-"/>
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<value name="LRZ_Q_CACHE_INVALIDATE" value="0x29" variants="A7XX-"/>
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<value name="BLIT_OP_SCALE_2D" value="0x2a" variants="A5XX-"/>
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<value name="CONTEXT_DONE_2D" value="0x2b" variants="A5XX-"/>
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<value name="VSC_BINNING_START" value="0x2c" variants="A5XX-"/>
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<value name="VSC_BINNING_END" value="0x2d" variants="A5XX-"/>
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<!-- a6xx events -->
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<doc>
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Invalidates UCHE.
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</doc>
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<value name="CACHE_INVALIDATE" value="49" variants="A6XX"/>
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<value name="CACHE_INVALIDATE" value="0x31" variants="A6XX"/>
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<value name="LABEL" value="63" variants="A6XX-"/>
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<value name="LABEL" value="0x3f" variants="A6XX-"/>
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<!-- note, some of these are the same as a6xx, just named differently -->
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<doc> Doesn't seem to do anything </doc>
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<value name="DUMMY_EVENT" value="1" variants="A7XX-"/>
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<value name="CCU_INVALIDATE_DEPTH" value="24" variants="A7XX-"/>
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<value name="CCU_INVALIDATE_COLOR" value="25" variants="A7XX-"/>
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<value name="CCU_RESOLVE_CLEAN" value="26" variants="A7XX-"/>
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<value name="CCU_FLUSH_DEPTH" value="28" variants="A7XX-"/>
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<value name="CCU_FLUSH_COLOR" value="29" variants="A7XX-"/>
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<value name="CCU_RESOLVE" value="30" variants="A7XX-"/>
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<value name="CCU_END_RESOLVE_GROUP" value="31" variants="A7XX-"/>
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<value name="CCU_CLEAN_DEPTH" value="32" variants="A7XX-"/>
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<value name="CCU_CLEAN_COLOR" value="33" variants="A7XX-"/>
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<value name="CACHE_RESET" value="48" variants="A7XX-"/>
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<value name="CACHE_CLEAN" value="49" variants="A7XX-"/>
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<value name="DUMMY_EVENT" value="0x01" variants="A7XX-"/>
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<value name="CCU_INVALIDATE_DEPTH" value="0x18" variants="A7XX-"/>
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<value name="CCU_INVALIDATE_COLOR" value="0x19" variants="A7XX-"/>
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<value name="CCU_RESOLVE_CLEAN" value="0x1a" variants="A7XX-"/>
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<value name="CCU_FLUSH_DEPTH" value="0x1c" variants="A7XX-"/>
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<value name="CCU_FLUSH_COLOR" value="0x1d" variants="A7XX-"/>
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<value name="CCU_RESOLVE" value="0x1e" variants="A7XX-"/>
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<value name="CCU_END_RESOLVE_GROUP" value="0x1f" variants="A7XX-"/>
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<value name="CCU_CLEAN_DEPTH" value="0x20" variants="A7XX-"/>
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<value name="CCU_CLEAN_COLOR" value="0x21" variants="A7XX-"/>
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<value name="CACHE_RESET" value="0x30" variants="A7XX-"/>
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<value name="CACHE_CLEAN" value="0x31" variants="A7XX-"/>
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<!-- TODO: deal with name conflicts with other gens -->
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<value name="CACHE_FLUSH7" value="50" variants="A7XX-"/>
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<value name="CACHE_INVALIDATE7" value="51" variants="A7XX-"/>
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<value name="CACHE_FLUSH7" value="0x32" variants="A7XX-"/>
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<value name="CACHE_INVALIDATE7" value="0x33" variants="A7XX-"/>
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<value name="DEPTH_BUFFER_FLIP" value="0x3d" variants="A8XX-"/>
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</enum>
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