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ir3: Limit CS lock/unlock quirk
We don't need this universally for everything >= gen7. Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
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4 changed files with 8 additions and 1 deletions
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@ -375,6 +375,9 @@ struct fd_dev_info {
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*/
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bool reading_shading_rate_requires_smask_quirk;
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/* Is lock/unlock sequence needed at end of compute shader? */
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bool cs_lock_unlock_quirk;
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/* Whether the ray_intersection instruction is present. */
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bool has_ray_intersection;
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@ -994,6 +994,7 @@ a7xx_gen1 = GPUProps(
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fs_must_have_non_zero_constlen_quirk = True,
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enable_tp_ubwc_flag_hint = True,
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reading_shading_rate_requires_smask_quirk = True,
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cs_lock_unlock_quirk = True,
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)
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a7xx_gen2 = GPUProps(
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@ -210,6 +210,9 @@ struct ir3_compiler {
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/* Whether half register shared->non-shared moves are broken. */
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bool mov_half_shared_quirk;
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/* Is lock/unlock sequence needed for CS? */
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bool cs_lock_unlock_quirk;
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/* Whether movs is supported for subgroupBroadcast. */
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bool has_movs;
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@ -6035,7 +6035,7 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler,
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*/
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IR3_PASS(ir, ir3_legalize, so, &max_bary);
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if (ctx->compiler->gen >= 7 && so->type == MESA_SHADER_COMPUTE) {
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if (ctx->compiler->cs_lock_unlock_quirk && so->type == MESA_SHADER_COMPUTE) {
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struct ir3_instruction *end = ir3_find_end(so->ir);
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struct ir3_instruction *lock =
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ir3_build_instr(&ctx->build, OPC_LOCK, 0, 0);
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