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freedreno/a6xx: Be more precise about CP_SET_MARKER

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Set the mode before we start emitting registers.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
This commit is contained in:
Rob Clark 2025-11-03 08:01:10 -08:00 • committed by Marge Bot
parent e0b6f97b9c
commit d30a14b726
3 changed files with 22 additions and 6 deletions
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6
src/gallium/drivers/freedreno/a6xx/fd6_blitter.cc
View file

@ -267,6 +267,9 @@ emit_setup(struct fd_context *ctx, fd_cs &cs)
FD6_FLUSH_CCU_DEPTH |
FD6_INVALIDATE_CCU_DEPTH);
fd_pkt7(cs, CP_SET_MARKER, 1)
.add(A6XX_CP_SET_MARKER_0_MODE(RM6_BLIT2DSCALE));
/* normal BLIT_OP_SCALE operation needs bypass RB_CCU_CNTL */
fd6_emit_gmem_cache_cntl<CHIP>(cs, ctx->screen, false);
}
@ -502,6 +505,9 @@ fd6_clear_ubwc(struct fd_batch *batch, struct fd_resource *rsc) assert_dt
{
fd_cs cs(fd_batch_get_prologue(batch));
fd_pkt7(cs, CP_SET_MARKER, 1)
.add(A6XX_CP_SET_MARKER_0_MODE(RM6_BLIT2DSCALE));
clear_ubwc_setup<CHIP>(cs);
unsigned size = rsc->layout.slices[0].offset;

9
src/gallium/drivers/freedreno/a6xx/fd6_compute.cc
View file

@ -156,7 +156,6 @@ static void
fd6_launch_grid(struct fd_context *ctx, const struct pipe_grid_info *info) in_dt
{
struct fd6_compute_state *cp = (struct fd6_compute_state *)ctx->compute;
fd_cs cs(ctx->batch->draw);
if (unlikely(!cp->v)) {
struct ir3_shader_state *hwcso = (struct ir3_shader_state *)cp->hwcso;
@ -173,6 +172,11 @@ fd6_launch_grid(struct fd_context *ctx, const struct pipe_grid_info *info) in_dt
fd6_emit_shader<CHIP>(ctx, cs, cp->v);
}
fd_cs cs(ctx->batch->draw);
fd_pkt7(cs, CP_SET_MARKER, 1)
.add(A6XX_CP_SET_MARKER_0_MODE(RM6_COMPUTE));
trace_start_compute(&ctx->batch->trace, cs, !!info->indirect, info->work_dim,
info->block[0], info->block[1], info->block[2],
info->grid[0], info->grid[1], info->grid[2],
@ -213,9 +217,6 @@ fd6_launch_grid(struct fd_context *ctx, const struct pipe_grid_info *info) in_dt
if (cp->v->need_driver_params)
fd6_emit_cs_driver_params<CHIP>(ctx, cs, cp->v, info);
fd_pkt7(cs, CP_SET_MARKER, 1)
.add(A6XX_CP_SET_MARKER_0_MODE(RM6_COMPUTE));
const unsigned *local_size =
info->block; // v->shader->nir->info->workgroup_size;
const unsigned *num_groups = info->grid;

13
src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc
View file

@ -919,7 +919,6 @@ static void
emit_binning_pass(fd_cs &cs, struct fd_batch *batch) assert_dt
{
const struct fd_gmem_stateobj *gmem = batch->gmem_state;
struct fd_screen *screen = batch->ctx->screen;
assert(!batch->tessellation);
@ -984,7 +983,10 @@ emit_binning_pass(fd_cs &cs, struct fd_batch *batch) assert_dt
fd_pkt7(cs, CP_SET_MODE, 1)
.add(0x0);
fd6_emit_gmem_cache_cntl<CHIP>(cs, screen, true);
if (CHIP >= A7XX) {
fd_pkt7(cs, CP_SET_MARKER, 1)
.add(A6XX_CP_SET_MARKER_0_MODE(RM7_BIN_VISIBILITY_END));
}
}
/* nregs: 7 */
@ -1940,6 +1942,9 @@ emit_sysmem_clears(fd_cs &cs, struct fd_batch *batch, struct fd_batch_subpass *s
trace_start_clears(&batch->trace, cs, buffers);
fd_pkt7(cs, CP_SET_MARKER, 1)
.add(A6XX_CP_SET_MARKER_0_MODE(RM6_BLIT2DSCALE));
if (buffers & PIPE_CLEAR_COLOR) {
for (int i = 0; i < pfb->nr_cbufs; i++) {
union pipe_color_union color = subpass->clear_color[i];
@ -1953,6 +1958,7 @@ emit_sysmem_clears(fd_cs &cs, struct fd_batch *batch, struct fd_batch_subpass *s
fd6_clear_surface<CHIP>(ctx, cs, &pfb->cbufs[i], &box2d, &color, 0);
}
}
if (buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)) {
union pipe_color_union value = {};
@ -2011,6 +2017,9 @@ fd6_emit_sysmem_prep(struct fd_batch *batch) assert_dt
if (batch->nondraw)
return;
fd_pkt7(cs, CP_SET_MARKER, 1)
.add(A6XX_CP_SET_MARKER_0_MODE(RM6_DIRECT_RENDER));
struct pipe_framebuffer_state *pfb = &batch->framebuffer;
if (pfb->width > 0 && pfb->height > 0)