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ir3: Fix cat3 latency

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The rule about only needing two cycles for 3rd src of cat3 instructions
only applies to variants of mad.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
This commit is contained in:
Rob Clark 2025-11-01 12:41:45 -07:00 • committed by Marge Bot
parent 02a4cc622d
commit e00bff2513
1 changed files with 2 additions and 5 deletions
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7
src/freedreno/ir3/ir3_delay.c
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@ -37,12 +37,9 @@ ir3_src_read_delay(struct ir3_compiler *compiler, struct ir3_instruction *instr,
return src_n;
}
/* cat3 instructions consume their last source one or two cycles later. Note
* that not all cat3 instructions seem to do this pre-a7xx.
/* mad instructions consume their last source one or two cycles later
*/
bool cat3_reads_later = compiler->gen >= 7
? (opc_cat(instr->opc) == 3)
: (is_mad(instr->opc) || is_madsh(instr->opc));
bool cat3_reads_later = (is_mad(instr->opc) || is_madsh(instr->opc));
if (cat3_reads_later && src_n == 2) {
return compiler->delay_slots.cat3_src2_read;
}