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freedreno: flip template param order

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Prep for next patch.  We need the per-gen CHIP template param to be
last.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
This commit is contained in:
Rob Clark 2025-10-21 16:33:49 -07:00 • committed by Marge Bot
parent b2349354e3
commit fb6dccc64c
5 changed files with 22 additions and 22 deletions
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20
src/gallium/drivers/freedreno/a6xx/fd6_const.cc
View file

@ -335,7 +335,7 @@ emit_user_consts(const struct ir3_shader_variant *v, fd_cs &cs,
ir3_emit_user_consts(v, cs.ring(), constbuf);
}
template <chip CHIP, fd6_pipeline_type PIPELINE>
template <fd6_pipeline_type PIPELINE, chip CHIP>
struct fd_ringbuffer *
fd6_build_user_consts(struct fd6_emit *emit)
{
@ -359,10 +359,10 @@ fd6_build_user_consts(struct fd6_emit *emit)
return constobj.ring();
}
template struct fd_ringbuffer * fd6_build_user_consts<A6XX, HAS_TESS_GS>(struct fd6_emit *emit);
template struct fd_ringbuffer * fd6_build_user_consts<A7XX, HAS_TESS_GS>(struct fd6_emit *emit);
template struct fd_ringbuffer * fd6_build_user_consts<A6XX, NO_TESS_GS>(struct fd6_emit *emit);
template struct fd_ringbuffer * fd6_build_user_consts<A7XX, NO_TESS_GS>(struct fd6_emit *emit);
template struct fd_ringbuffer * fd6_build_user_consts<HAS_TESS_GS, A6XX>(struct fd6_emit *emit);
template struct fd_ringbuffer * fd6_build_user_consts<HAS_TESS_GS, A7XX>(struct fd6_emit *emit);
template struct fd_ringbuffer * fd6_build_user_consts<NO_TESS_GS, A6XX>(struct fd6_emit *emit);
template struct fd_ringbuffer * fd6_build_user_consts<NO_TESS_GS, A7XX>(struct fd6_emit *emit);
template <chip CHIP>
static inline void
@ -401,7 +401,7 @@ emit_hs_driver_params(const struct ir3_shader_variant *v, fd_cs &dpconstobj,
}
}
template <chip CHIP, fd6_pipeline_type PIPELINE>
template <fd6_pipeline_type PIPELINE, chip CHIP>
struct fd_ringbuffer *
fd6_build_driver_params(struct fd6_emit *emit)
{
@ -467,10 +467,10 @@ fd6_build_driver_params(struct fd6_emit *emit)
return dpconstobj.ring();
}
template struct fd_ringbuffer * fd6_build_driver_params<A6XX, HAS_TESS_GS>(struct fd6_emit *emit);
template struct fd_ringbuffer * fd6_build_driver_params<A7XX, HAS_TESS_GS>(struct fd6_emit *emit);
template struct fd_ringbuffer * fd6_build_driver_params<A6XX, NO_TESS_GS>(struct fd6_emit *emit);
template struct fd_ringbuffer * fd6_build_driver_params<A7XX, NO_TESS_GS>(struct fd6_emit *emit);
template struct fd_ringbuffer * fd6_build_driver_params<HAS_TESS_GS, A6XX>(struct fd6_emit *emit);
template struct fd_ringbuffer * fd6_build_driver_params<HAS_TESS_GS, A7XX>(struct fd6_emit *emit);
template struct fd_ringbuffer * fd6_build_driver_params<NO_TESS_GS, A6XX>(struct fd6_emit *emit);
template struct fd_ringbuffer * fd6_build_driver_params<NO_TESS_GS, A7XX>(struct fd6_emit *emit);
template <chip CHIP>
void

4
src/gallium/drivers/freedreno/a6xx/fd6_const.h
View file

@ -14,10 +14,10 @@ struct fd_ringbuffer *fd6_build_tess_consts(struct fd6_emit *emit) assert_dt;
template <chip CHIP>
unsigned fd6_user_consts_cmdstream_size(const struct ir3_shader_variant *v);
template <chip CHIP, fd6_pipeline_type PIPELINE>
template <fd6_pipeline_type PIPELINE, chip CHIP>
struct fd_ringbuffer *fd6_build_user_consts(struct fd6_emit *emit) assert_dt;
template <chip CHIP, fd6_pipeline_type PIPELINE>
template <fd6_pipeline_type PIPELINE, chip CHIP>
struct fd_ringbuffer *
fd6_build_driver_params(struct fd6_emit *emit) assert_dt;

4
src/gallium/drivers/freedreno/a6xx/fd6_draw.cc
View file

@ -461,7 +461,7 @@ draw_vbos(struct fd_context *ctx, const struct pipe_draw_info *info,
}
if (emit.dirty_groups)
fd6_emit_3d_state<CHIP, PIPELINE>(cs, &emit);
fd6_emit_3d_state<PIPELINE, CHIP>(cs, &emit);
/* All known firmware versions do not wait for WFI's with CP_DRAW_AUTO.
* Plus, for the common case where the counter buffer is written by
@ -539,7 +539,7 @@ draw_vbos(struct fd_context *ctx, const struct pipe_draw_info *info,
emit.state.num_groups = 0;
emit.draw = &draws[i];
emit.draw_id = info->increment_draw_id ? i : 0;
fd6_emit_3d_state<CHIP, PIPELINE>(cs, &emit);
fd6_emit_3d_state<PIPELINE, CHIP>(cs, &emit);
}
assert(!index_offset); /* handled by util_draw_multi() */

14
src/gallium/drivers/freedreno/a6xx/fd6_emit.cc
View file

@ -552,7 +552,7 @@ build_prim_mode(struct fd6_emit *emit, struct fd_context *ctx, bool gmem)
.ring();
}
template <chip CHIP, fd6_pipeline_type PIPELINE>
template <fd6_pipeline_type PIPELINE, chip CHIP>
void
fd6_emit_3d_state(fd_cs &cs, struct fd6_emit *emit)
{
@ -655,11 +655,11 @@ fd6_emit_3d_state(fd_cs &cs, struct fd6_emit *emit)
fd6_state_take_group(&emit->state, state, FD6_GROUP_FS_BINDLESS);
break;
case FD6_GROUP_CONST:
state = fd6_build_user_consts<CHIP, PIPELINE>(emit);
state = fd6_build_user_consts<PIPELINE, CHIP>(emit);
fd6_state_take_group(&emit->state, state, FD6_GROUP_CONST);
break;
case FD6_GROUP_DRIVER_PARAMS:
state = fd6_build_driver_params<CHIP, PIPELINE>(emit);
state = fd6_build_driver_params<PIPELINE, CHIP>(emit);
fd6_state_take_group(&emit->state, state, FD6_GROUP_DRIVER_PARAMS);
break;
case FD6_GROUP_PRIMITIVE_PARAMS:
@ -710,10 +710,10 @@ fd6_emit_3d_state(fd_cs &cs, struct fd6_emit *emit)
fd6_state_emit(&emit->state, cs);
}
template void fd6_emit_3d_state<A6XX, NO_TESS_GS>(fd_cs &cs, struct fd6_emit *emit);
template void fd6_emit_3d_state<A7XX, NO_TESS_GS>(fd_cs &cs, struct fd6_emit *emit);
template void fd6_emit_3d_state<A6XX, HAS_TESS_GS>(fd_cs &cs, struct fd6_emit *emit);
template void fd6_emit_3d_state<A7XX, HAS_TESS_GS>(fd_cs &cs, struct fd6_emit *emit);
template void fd6_emit_3d_state<NO_TESS_GS, A6XX>(fd_cs &cs, struct fd6_emit *emit);
template void fd6_emit_3d_state<NO_TESS_GS, A7XX>(fd_cs &cs, struct fd6_emit *emit);
template void fd6_emit_3d_state<HAS_TESS_GS, A6XX>(fd_cs &cs, struct fd6_emit *emit);
template void fd6_emit_3d_state<HAS_TESS_GS, A7XX>(fd_cs &cs, struct fd6_emit *emit);
template <chip CHIP>
void

2
src/gallium/drivers/freedreno/a6xx/fd6_emit.h
View file

@ -353,7 +353,7 @@ fd6_gl2spacing(enum gl_tess_spacing spacing)
}
}
template <chip CHIP, fd6_pipeline_type PIPELINE>
template <fd6_pipeline_type PIPELINE, chip CHIP>
void fd6_emit_3d_state(fd_cs &cs, struct fd6_emit *emit) assert_dt;
struct fd6_compute_state;