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freedreno/a6xx: Actually use lrz fast clear

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Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
This commit is contained in:
Rob Clark 2025-11-03 12:31:27 -08:00 • committed by Marge Bot
parent d30a14b726
commit b1218926bc
2 changed files with 39 additions and 31 deletions
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38
src/gallium/drivers/freedreno/a6xx/fd6_emit.cc
View file

@ -225,35 +225,19 @@ build_lrz(struct fd6_emit *emit) assert_dt
fd6_ctx->last.lrz = lrz;
unsigned nregs = (CHIP >= A7XX) ? 5 : 4;
unsigned nregs = 4;
fd_crb crb(ctx->batch->submit, nregs);
if (CHIP >= A7XX) {
crb.add(GRAS_LRZ_CNTL(CHIP,
.enable = lrz.enable,
.lrz_write = lrz.write,
.greater = lrz.direction == FD_LRZ_GREATER,
.z_write_enable = lrz.test,
.z_bounds_enable = lrz.z_bounds_enable,
))
.add(GRAS_LRZ_CNTL2(CHIP,
.disable_on_wrong_dir = false,
.fc_enable = false,
));
} else {
crb.add(GRAS_LRZ_CNTL(CHIP,
.enable = lrz.enable,
.lrz_write = lrz.write,
.greater = lrz.direction == FD_LRZ_GREATER,
.fc_enable = false,
.z_write_enable = lrz.test,
.z_bounds_enable = lrz.z_bounds_enable,
.disable_on_wrong_dir = false,
)
);
}
crb.add(A6XX_RB_LRZ_CNTL(.enable = lrz.enable, ))
crb.add(GRAS_LRZ_CNTL(CHIP,
.enable = lrz.enable,
.lrz_write = lrz.write,
.greater = lrz.direction == FD_LRZ_GREATER,
.fc_enable = false, /* a6xx only */
.z_write_enable = lrz.test,
.z_bounds_enable = lrz.z_bounds_enable,
.disable_on_wrong_dir = false, /* a6xx only */
))
.add(A6XX_RB_LRZ_CNTL(.enable = lrz.enable, ))
.add(A6XX_RB_DEPTH_PLANE_CNTL(.z_mode = lrz.z_mode, ))
.add(GRAS_SU_DEPTH_PLANE_CNTL(CHIP, .z_mode = lrz.z_mode, ));

32
src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc
View file

@ -221,6 +221,15 @@ emit_zs(fd_crb &crb, struct pipe_surface *zsbuf, const struct fd_gmem_stateobj *
}
}
template <chip CHIP>
static inline bool
lrzfc_enabled(struct fd_resource *zsbuf)
{
if ((CHIP < A7XX) || FD_DBG(NOLRZFC) || !zsbuf)
return false;
return zsbuf->lrz_layout.lrz_fc_size > 0;
}
template <chip CHIP>
static void
emit_lrz(fd_cs &cs, struct fd_batch *batch, struct fd_batch_subpass *subpass)
@ -228,13 +237,17 @@ emit_lrz(fd_cs &cs, struct fd_batch *batch, struct fd_batch_subpass *subpass)
struct pipe_framebuffer_state *pfb = &batch->framebuffer;
if (!subpass->lrz) {
fd_crb crb(cs, 6);
fd_crb crb(cs, 7);
crb.add(GRAS_LRZ_BUFFER_BASE(CHIP));
crb.add(GRAS_LRZ_BUFFER_PITCH(CHIP));
crb.add(A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE());
if (CHIP >= A7XX)
if (CHIP >= A7XX) {
crb.add(GRAS_LRZ_DEPTH_BUFFER_INFO(CHIP));
crb.add(GRAS_LRZ_CNTL2(CHIP));
}
return;
}
@ -246,7 +259,7 @@ emit_lrz(fd_cs &cs, struct fd_batch *batch, struct fd_batch_subpass *subpass)
*/
fd6_event_write<CHIP>(batch->ctx, cs, FD_LRZ_FLUSH);
fd_crb crb(cs, 6);
fd_crb crb(cs, 7);
struct fd_resource *zsbuf = fd_resource(pfb->zsbuf.texture);
@ -263,6 +276,10 @@ emit_lrz(fd_cs &cs, struct fd_batch *batch, struct fd_batch_subpass *subpass)
crb.add(GRAS_LRZ_DEPTH_BUFFER_INFO(CHIP,
.depth_format = fd6_pipe2depth(pfb->zsbuf.format),
));
crb.add(GRAS_LRZ_CNTL2(CHIP,
.disable_on_wrong_dir = false,
.fc_enable = lrzfc_enabled<CHIP>(zsbuf),
));
}
}
@ -308,7 +325,14 @@ emit_lrz_clears(struct fd_batch *batch)
fd6_set_rb_dbg_eco_mode<CHIP>(ctx, cs, true);
}
fd6_clear_lrz<CHIP>(cs, zsbuf, subpass->lrz, subpass->clear_depth);
if (lrzfc_enabled<CHIP>(zsbuf)) {
emit_lrz<CHIP>(cs, batch, subpass);
fd_pkt4(cs, 1)
.add(GRAS_LRZ_DEPTH_CLEAR(CHIP, subpass->clear_depth));
fd6_event_write<CHIP>(ctx, cs, FD_LRZ_CLEAR);
} else {
fd6_clear_lrz<CHIP>(cs, zsbuf, subpass->lrz, subpass->clear_depth);
}
count++;
}