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freedreno: More ergonomic cs casting

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Make it less awkward to bridge back to legacy cmdstream builder.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
This commit is contained in:
Rob Clark 2025-11-02 07:05:55 -08:00 • committed by Marge Bot
parent a24f3efd98
commit 1a22daa157
14 changed files with 60 additions and 63 deletions
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6
src/freedreno/common/fd6_pack.h
View file

@ -142,7 +142,7 @@ public:
}
/* bridge back to the legacy world: */
struct fd_ringbuffer *ring() {
operator struct fd_ringbuffer *() {
check_flush();
return ring_;
}
@ -176,7 +176,7 @@ private:
*/
class fd_pkt4 : public fd_ringbuffer_builder {
public:
fd_pkt4(fd_cs &cs, unsigned nregs) : fd_ringbuffer_builder(cs.ring()) {
fd_pkt4(fd_cs &cs, unsigned nregs) : fd_ringbuffer_builder(cs) {
init(nregs);
}
@ -308,7 +308,7 @@ protected:
public:
/* Bridge to the legacy world, ideally we can remove this eventually: */
struct fd_ringbuffer *ring() {
operator struct fd_ringbuffer *() {
return ring_;
}

2
src/gallium/drivers/freedreno/a6xx/fd6_blend.cc
View file

@ -124,7 +124,7 @@ __fd6_setup_blend_variant(struct fd6_blend_stateobj *blend,
.sample_mask = sample_mask,
));
so->stateobj = crb.ring();
so->stateobj = crb;
so->sample_mask = sample_mask;
util_dynarray_append(&blend->variants, so);

4
src/gallium/drivers/freedreno/a6xx/fd6_blitter.cc
View file

@ -1275,7 +1275,7 @@ handle_rgba_blit(struct fd_context *ctx, const struct pipe_blit_info *info)
DBG_BLIT(info, batch);
trace_start_blit(&batch->trace, cs.ring(), info->src.resource->target,
trace_start_blit(&batch->trace, cs, info->src.resource->target,
info->dst.resource->target);
if ((info->src.resource->target == PIPE_BUFFER) &&
@ -1290,7 +1290,7 @@ handle_rgba_blit(struct fd_context *ctx, const struct pipe_blit_info *info)
emit_blit_texture<CHIP>(ctx, cs, info);
}
trace_end_blit(&batch->trace, cs.ring());
trace_end_blit(&batch->trace, cs);
fd6_emit_flushes<CHIP>(batch->ctx, cs,
FD6_FLUSH_CCU_COLOR |

4
src/gallium/drivers/freedreno/a6xx/fd6_compute.cc
View file

@ -173,7 +173,7 @@ fd6_launch_grid(struct fd_context *ctx, const struct pipe_grid_info *info) in_dt
fd6_emit_shader<CHIP>(ctx, cs, cp->v);
}
trace_start_compute(&ctx->batch->trace, cs.ring(), !!info->indirect, info->work_dim,
trace_start_compute(&ctx->batch->trace, cs, !!info->indirect, info->work_dim,
info->block[0], info->block[1], info->block[2],
info->grid[0], info->grid[1], info->grid[2],
cp->v->shader_id);
@ -289,7 +289,7 @@ fd6_launch_grid(struct fd_context *ctx, const struct pipe_grid_info *info) in_dt
.add(CP_EXEC_CS_3(info->grid[2]));
}
trace_end_compute(&ctx->batch->trace, cs.ring());
trace_end_compute(&ctx->batch->trace, cs);
fd_context_all_clean(ctx);
}

22
src/gallium/drivers/freedreno/a6xx/fd6_const.cc
View file

@ -256,7 +256,7 @@ fd6_build_tess_consts(struct fd6_emit *emit)
gs_params, ARRAY_SIZE(gs_params));
}
return constobj.ring();
return constobj;
}
FD_GENX(fd6_build_tess_consts);
@ -332,7 +332,7 @@ emit_user_consts(const struct ir3_shader_variant *v, fd_cs &cs,
if (CHIP == A7XX && v->compiler->load_shader_consts_via_preamble)
return;
ir3_emit_user_consts(v, cs.ring(), constbuf);
ir3_emit_user_consts(v, cs, constbuf);
}
template <fd6_pipeline_type PIPELINE, chip CHIP>
@ -357,7 +357,7 @@ fd6_build_user_consts(struct fd6_emit *emit)
}
emit_user_consts<CHIP>(emit->fs, constobj, &ctx->constbuf[MESA_SHADER_FRAGMENT]);
return constobj.ring();
return constobj;
}
FD_GENX2(fd6_build_user_consts, fd6_pipeline_type, NO_TESS_GS);
FD_GENX2(fd6_build_user_consts, fd6_pipeline_type, HAS_TESS_GS);
@ -377,7 +377,7 @@ emit_driver_params(const struct ir3_shader_variant *v, fd_cs &dpconstobj,
dword_sizeof(*vertex_params),
vertex_params);
} else {
ir3_emit_driver_params(v, dpconstobj.ring(), ctx, info, indirect, vertex_params);
ir3_emit_driver_params(v, dpconstobj, ctx, info, indirect, vertex_params);
}
}
@ -395,7 +395,7 @@ emit_hs_driver_params(const struct ir3_shader_variant *v, fd_cs &dpconstobj,
dword_sizeof(hs_params),
&hs_params);
} else {
ir3_emit_hs_driver_params(v, dpconstobj.ring(), ctx);
ir3_emit_hs_driver_params(v, dpconstobj, ctx);
}
}
@ -440,7 +440,7 @@ fd6_build_driver_params(struct fd6_emit *emit)
/* VS still works the old way*/
if (emit->vs->need_driver_params) {
ir3_emit_driver_params(emit->vs, dpconstobj.ring(), ctx, emit->info, emit->indirect, &p);
ir3_emit_driver_params(emit->vs, dpconstobj, ctx, emit->info, emit->indirect, &p);
}
if (PIPELINE == HAS_TESS_GS) {
@ -462,7 +462,7 @@ fd6_build_driver_params(struct fd6_emit *emit)
fd6_ctx->has_dp_state = true;
return dpconstobj.ring();
return dpconstobj;
}
FD_GENX2(fd6_build_driver_params, fd6_pipeline_type, NO_TESS_GS);
FD_GENX2(fd6_build_driver_params, fd6_pipeline_type, HAS_TESS_GS);
@ -490,7 +490,7 @@ fd6_emit_cs_driver_params(struct fd_context *ctx, fd_cs &cs,
if (info->indirect) {
/* Copy indirect params into UBO: */
ctx->screen->mem_to_mem(cs.ring(), buffer, buffer_offset, info->indirect,
ctx->screen->mem_to_mem(cs, buffer, buffer_offset, info->indirect,
info->indirect_offset, 3);
wait_mem_writes(ctx);
@ -503,7 +503,7 @@ fd6_emit_cs_driver_params(struct fd_context *ctx, fd_cs &cs,
pipe_resource_reference(&buffer, NULL);
} else {
ir3_emit_cs_driver_params(v, cs.ring(), ctx, info);
ir3_emit_cs_driver_params(v, cs, ctx, info);
if (info->indirect)
wait_mem_writes(ctx);
}
@ -535,7 +535,7 @@ fd6_emit_immediates(const struct ir3_shader_variant *v, fd_cs &cs)
if (CHIP == A7XX && v->compiler->load_inline_uniforms_via_preamble_ldgk)
return;
ir3_emit_immediates(v, cs.ring());
ir3_emit_immediates(v, cs);
}
FD_GENX(fd6_emit_immediates);
@ -552,7 +552,7 @@ fd6_emit_link_map(struct fd_context *ctx, fd_cs &cs,
fd6_upload_emit_driver_ubo(ctx, cs, consumer, base, size, producer->output_loc);
} else {
ir3_emit_link_map(producer, consumer, cs.ring());
ir3_emit_link_map(producer, consumer, cs);
}
}
FD_GENX(fd6_emit_link_map);

6
src/gallium/drivers/freedreno/a6xx/fd6_context.cc
View file

@ -102,7 +102,7 @@ fd6_vertex_state_create(struct pipe_context *pctx, unsigned num_elements,
crb.add(A6XX_VFD_VERTEX_BUFFER_STRIDE(elem->vertex_buffer_index, elem->src_stride));
}
state->stateobj = crb.ring();
state->stateobj = crb;
return state;
}
@ -313,13 +313,13 @@ fd6_context_create(struct pipe_screen *pscreen, void *priv,
.add(A6XX_RB_MSAA_SAMPLE_POS_CNTL())
.add(TPL1_MSAA_SAMPLE_POS_CNTL(CHIP));
fd6_ctx->sample_locations_disable_stateobj = crb.ring();
fd6_ctx->sample_locations_disable_stateobj = crb;
fd6_ctx->preamble = fd6_build_preemption_preamble<CHIP>(&fd6_ctx->base);
fd_cs restore(fd6_ctx->base.pipe, 0x1000);
fd6_emit_static_regs<CHIP>(restore, &fd6_ctx->base);
fd6_ctx->restore = restore.ring();
fd6_ctx->restore = restore;
return fd_context_init_tc(pctx, flags);
}

21
src/gallium/drivers/freedreno/a6xx/fd6_emit.cc
View file

@ -72,7 +72,7 @@ build_vbo_state(struct fd6_emit *emit) assert_dt
}
}
return crb.ring();
return crb;
}
static enum a6xx_ztest_mode
@ -257,7 +257,7 @@ build_lrz(struct fd6_emit *emit) assert_dt
.add(A6XX_RB_DEPTH_PLANE_CNTL(.z_mode = lrz.z_mode, ))
.add(GRAS_SU_DEPTH_PLANE_CNTL(CHIP, .z_mode = lrz.z_mode, ));
return crb.ring();
return crb;
}
template <chip CHIP>
@ -275,7 +275,7 @@ build_scissor(struct fd6_emit *emit) assert_dt
.add(GRAS_SC_SCREEN_SCISSOR_BR(CHIP, i, .x = scissors[i].maxx, .y = scissors[i].maxy));
}
return crb.ring();
return crb;
}
/* Combination of FD_DIRTY_FRAMEBUFFER | FD_DIRTY_RASTERIZER_DISCARD |
@ -326,7 +326,7 @@ build_prog_fb_rast(struct fd6_emit *emit) assert_dt
crb.add(A6XX_SP_PS_OUTPUT_MASK(.dword = mrt_components))
.add(A6XX_RB_PS_OUTPUT_MASK(.dword = mrt_components));
return crb.ring();
return crb;
}
static struct fd_ringbuffer *
@ -339,8 +339,7 @@ build_blend_color(struct fd6_emit *emit) assert_dt
.add(A6XX_RB_BLEND_CONSTANT_RED_FP32(bcolor->color[0]))
.add(A6XX_RB_BLEND_CONSTANT_GREEN_FP32(bcolor->color[1]))
.add(A6XX_RB_BLEND_CONSTANT_BLUE_FP32(bcolor->color[2]))
.add(A6XX_RB_BLEND_CONSTANT_ALPHA_FP32(bcolor->color[3]))
.ring();
.add(A6XX_RB_BLEND_CONSTANT_ALPHA_FP32(bcolor->color[3]));
}
template <chip CHIP>
@ -374,8 +373,7 @@ build_sample_locations(struct fd6_emit *emit)
.add(A6XX_RB_MSAA_SAMPLE_POS_CNTL(.location_enable = true))
.add(A6XX_RB_PROGRAMMABLE_MSAA_POS_0(.dword = sample_locations))
.add(TPL1_MSAA_SAMPLE_POS_CNTL(CHIP, .location_enable = true))
.add(A6XX_TPL1_PROGRAMMABLE_MSAA_POS_0(.dword = sample_locations))
.ring();
.add(A6XX_TPL1_PROGRAMMABLE_MSAA_POS_0(.dword = sample_locations));
}
template <chip CHIP>
@ -548,8 +546,7 @@ build_prim_mode(struct fd6_emit *emit, struct fd_context *ctx, bool gmem)
.add(GRAS_SC_CNTL(CHIP,
.ccusinglecachelinesize = 2,
.single_prim_mode = (enum a6xx_single_prim_mode)prim_mode)
)
.ring();
);
}
template <fd6_pipeline_type PIPELINE, chip CHIP>
@ -1065,7 +1062,7 @@ fd6_emit_restore(fd_cs &cs, struct fd_batch *batch)
struct fd_screen *screen = ctx->screen;
if (!batch->nondraw) {
trace_start_state_restore(&batch->trace, cs.ring());
trace_start_state_restore(&batch->trace, cs);
}
if (FD_DBG(STOMP)) {
@ -1125,7 +1122,7 @@ fd6_emit_restore(fd_cs &cs, struct fd_batch *batch)
.add(CP_SET_AMBLE_2(.type = POSTAMBLE_AMBLE_TYPE));
if (!batch->nondraw) {
trace_end_state_restore(&batch->trace, cs.ring());
trace_end_state_restore(&batch->trace, cs);
}
}
FD_GENX(fd6_emit_restore);

36
src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc
View file

@ -813,7 +813,7 @@ emit_conditional_ib(fd_cs &cs, struct fd_batch *batch, const struct fd_tile *til
unsigned count = fd_ringbuffer_cmd_count(target);
BEGIN_RING(cs.ring(), 5 + 4 * count); /* ensure conditional doesn't get split */
BEGIN_RING(cs, 5 + 4 * count); /* ensure conditional doesn't get split */
fd_pkt7(cs, CP_REG_TEST, 1)
.add(A6XX_CP_REG_TEST_0(
@ -954,12 +954,12 @@ emit_binning_pass(fd_cs &cs, struct fd_batch *batch) assert_dt
.add(A6XX_TPL1_WINDOW_OFFSET(.x = 0, .y = 0));
/* emit IB to binning drawcmds: */
trace_start_binning_ib(&batch->trace, cs.ring());
trace_start_binning_ib(&batch->trace, cs);
foreach_subpass (subpass, batch) {
emit_lrz<CHIP>(cs, batch, subpass);
fd6_emit_ib<CHIP>(cs, subpass->draw);
}
trace_end_binning_ib(&batch->trace, cs.ring());
trace_end_binning_ib(&batch->trace, cs);
fd_pkt7(cs, CP_SET_DRAW_STATE, 3)
.add(CP_SET_DRAW_STATE__0(0, .disable_all_groups = true))
@ -980,9 +980,9 @@ emit_binning_pass(fd_cs &cs, struct fd_batch *batch) assert_dt
FD6_WAIT_FOR_IDLE |
FD6_WAIT_FOR_ME);
trace_start_vsc_overflow_test(&batch->trace, cs.ring());
trace_start_vsc_overflow_test(&batch->trace, cs);
emit_vsc_overflow_test(batch);
trace_end_vsc_overflow_test(&batch->trace, cs.ring());
trace_end_vsc_overflow_test(&batch->trace, cs);
fd_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1)
.add(0x0);
@ -1067,7 +1067,7 @@ fd6_build_preemption_preamble(struct fd_context *ctx)
control_ptr(fd6_context(ctx), vsc_state),
));
return cs.ring();
return cs;
}
FD_GENX(fd6_build_preemption_preamble);
@ -1088,9 +1088,9 @@ fd6_emit_tile_init(struct fd_batch *batch) assert_dt
fd6_event_write<CHIP>(batch->ctx, cs, FD_LRZ_FLUSH);
if (batch->prologue) {
trace_start_prologue(&batch->trace, cs.ring());
trace_start_prologue(&batch->trace, cs);
fd6_emit_ib<CHIP>(cs, batch->prologue);
trace_end_prologue(&batch->trace, cs.ring());
trace_end_prologue(&batch->trace, cs);
}
fd6_cache_inv<CHIP>(batch->ctx, cs);
@ -1655,9 +1655,9 @@ fd6_emit_tile_renderprep(struct fd_batch *batch, const struct fd_tile *tile)
{
if (batch->tile_loads) {
fd_cs cs(batch->gmem);
trace_start_tile_loads(&batch->trace, cs.ring(), batch->restore);
trace_start_tile_loads(&batch->trace, cs, batch->restore);
emit_conditional_ib<CHIP>(cs, batch, tile, batch->tile_loads);
trace_end_tile_loads(&batch->trace, cs.ring());
trace_end_tile_loads(&batch->trace, cs);
}
}
@ -1829,9 +1829,9 @@ fd6_emit_tile(struct fd_batch *batch, const struct fd_tile *tile)
foreach_subpass (subpass, batch) {
if (subpass->subpass_clears) {
trace_start_clears(&batch->trace, cs.ring(), subpass->fast_cleared);
trace_start_clears(&batch->trace, cs, subpass->fast_cleared);
emit_conditional_ib<CHIP>(cs, batch, tile, subpass->subpass_clears);
trace_end_clears(&batch->trace, cs.ring());
trace_end_clears(&batch->trace, cs);
}
emit_lrz<CHIP>(cs, batch, subpass);
@ -1870,9 +1870,9 @@ fd6_emit_tile_gmem2mem(struct fd_batch *batch, const struct fd_tile *tile)
emit_marker6<CHIP>(cs, 7);
if (batch->tile_store) {
trace_start_tile_stores(&batch->trace, cs.ring(), batch->resolve);
trace_start_tile_stores(&batch->trace, cs, batch->resolve);
emit_conditional_ib<CHIP>(cs, batch, tile, batch->tile_store);
trace_end_tile_stores(&batch->trace, cs.ring());
trace_end_tile_stores(&batch->trace, cs);
}
fd_pkt7(cs, CP_SET_MARKER, 1)
@ -1914,7 +1914,7 @@ emit_sysmem_clears(fd_cs &cs, struct fd_batch *batch, struct fd_batch_subpass *s
struct pipe_box box2d;
u_box_2d(0, 0, pfb->width, pfb->height, &box2d);
trace_start_clears(&batch->trace, cs.ring(), buffers);
trace_start_clears(&batch->trace, cs, buffers);
if (buffers & PIPE_CLEAR_COLOR) {
for (int i = 0; i < pfb->nr_cbufs; i++) {
@ -1958,7 +1958,7 @@ emit_sysmem_clears(fd_cs &cs, struct fd_batch *batch, struct fd_batch_subpass *s
fd6_emit_flushes<CHIP>(ctx, cs, FD6_FLUSH_CCU_COLOR | FD6_INVALIDATE_CCU_COLOR);
trace_end_clears(&batch->trace, cs.ring());
trace_end_clears(&batch->trace, cs);
}
template <chip CHIP>
@ -1974,11 +1974,11 @@ fd6_emit_sysmem_prep(struct fd_batch *batch) assert_dt
if (batch->prologue) {
if (!batch->nondraw) {
trace_start_prologue(&batch->trace, cs.ring());
trace_start_prologue(&batch->trace, cs);
}
fd6_emit_ib<CHIP>(cs, batch->prologue);
if (!batch->nondraw) {
trace_end_prologue(&batch->trace, cs.ring());
trace_end_prologue(&batch->trace, cs);
}
}

2
src/gallium/drivers/freedreno/a6xx/fd6_image.cc
View file

@ -362,7 +362,7 @@ fd6_build_bindless_state(struct fd_context *ctx, mesa_shader_stage shader,
}
}
return cs.ring();
return cs;
}
FD_GENX(fd6_build_bindless_state);

12
src/gallium/drivers/freedreno/a6xx/fd6_program.cc
View file

@ -228,7 +228,7 @@ fd6_emit_shader(struct fd_context *ctx, fd_cs &cs, const struct ir3_shader_varia
/* Name should generally match what you get with MESA_SHADER_CAPTURE_PATH: */
const char *name = so->name;
if (name)
fd_emit_string5(cs.ring(), name, strlen(name));
fd_emit_string5(cs, name, strlen(name));
#endif
emit_shader_regs<CHIP>(ctx, cs, so);
@ -273,7 +273,7 @@ setup_stream_out_disable(struct fd_context *ctx)
crb.add(PC_DGEN_SO_CNTL(CHIP));
}
fd6_context(ctx)->streamout_disable_stateobj = crb.ring();
fd6_context(ctx)->streamout_disable_stateobj = crb;
}
template <chip CHIP>
@ -371,7 +371,7 @@ setup_stream_out(struct fd_context *ctx, struct fd6_program_state *state,
crb.add(PC_DGEN_SO_CNTL(CHIP, .stream_enable = true));
}
state->streamout_stateobj = crb.ring();
state->streamout_stateobj = crb;
}
static uint32_t
@ -434,7 +434,7 @@ setup_config_stateobj(struct fd_context *ctx, struct fd6_program_state *state)
crb.add(SP_GFX_USIZE(CHIP, ir3_shader_num_uavs(state->fs)));
state->config_stateobj = crb.ring();
state->config_stateobj = crb;
}
static inline uint32_t
@ -1317,7 +1317,7 @@ create_interp_stateobj(struct fd_context *ctx, struct fd6_program_state *state)
emit_interp_state<CHIP>(crb, state, false, false, 0);
return crb.ring();
return crb;
}
/* build the program streaming state which is not part of the pre-
@ -1339,7 +1339,7 @@ fd6_program_interp_state(struct fd6_emit *emit)
emit_interp_state<CHIP>(crb, state, emit->rasterflat,
emit->sprite_coord_mode, emit->sprite_coord_enable);
return crb.ring();
return crb;
}
}
FD_GENX(fd6_program_interp_state);

2
src/gallium/drivers/freedreno/a6xx/fd6_query.cc
View file

@ -236,7 +236,7 @@ occlusion_predicate_result_resource(struct fd_acc_query *aq, struct fd_ringbuffe
.add(1)
.add(0);
copy_result(cs.ring(), result_type, dst, offset, fd_resource(aq->prsc),
copy_result(cs, result_type, dst, offset, fd_resource(aq->prsc),
offsetof(struct fd6_query_sample, result));
}

2
src/gallium/drivers/freedreno/a6xx/fd6_rasterizer.cc
View file

@ -126,7 +126,7 @@ __fd6_setup_rasterizer_stateobj(struct fd_context *ctx,
crb.add(RB_UNKNOWN_8A30(CHIP));
}
return crb.ring();
return crb;
}
FD_GENX(__fd6_setup_rasterizer_stateobj);

2
src/gallium/drivers/freedreno/a6xx/fd6_texture.cc
View file

@ -711,7 +711,7 @@ build_texture_state(struct fd_context *ctx, mesa_shader_stage type,
fd_bo_del(tex_desc);
}
return cs.ring();
return cs;
}
/**

2
src/gallium/drivers/freedreno/a6xx/fd6_zsa.cc
View file

@ -232,7 +232,7 @@ fd6_zsa_state_create(struct pipe_context *pctx,
crb.add(A6XX_RB_DEPTH_BOUND_MAX(cso->depth_bounds_max));
}
so->stateobj[i] = crb.ring();
so->stateobj[i] = crb;
}
return so;