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ir3: Fix gen8 instruction timings

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non_alu is still 6.  But AFAICT none of this changes since a7xx so these
were probably wrong on a7xx as well.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
This commit is contained in:
Rob Clark 2025-10-21 10:36:13 -07:00 • committed by Marge Bot
parent 3e7f200e1f
commit 02a4cc622d
1 changed files with 3 additions and 2 deletions
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5
src/freedreno/ir3/ir3_compiler.c
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@ -268,8 +268,9 @@ ir3_compiler_create(struct fd_device *dev, const struct fd_dev_id *dev_id,
compiler->mergedregs = true;
compiler->has_sel_b_fneg = dev_info->props.has_sel_b_fneg;
if (compiler->gen >= 7) {
compiler->has_alias_tex = true;
compiler->has_alias_tex = (compiler->gen >= 7);
if (compiler->gen == 7) {
compiler->delay_slots.alu_to_alu = 2;
compiler->delay_slots.non_alu = 5;
compiler->delay_slots.cat3_src2_read = 1;