fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2025-12-27 23:30:10 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

freedreno/registers: Name RB_LRZ_CNTL2

Browse source 
We'll need this for LRZ flush sequence on gen8

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
This commit is contained in:
Rob Clark 2025-10-20 11:51:38 -07:00 • committed by Marge Bot
parent 5c1bcaca24
commit 843ec5dbe7
2 changed files with 8 additions and 6 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

10
src/freedreno/common/freedreno_devices.py
View file

@ -1060,7 +1060,7 @@ a730_raw_magic_regs = [
[A6XXRegs.REG_A6XX_GRAS_DBG_ECO_CNTL, 0x00000800],
[A6XXRegs.REG_A7XX_RB_UNKNOWN_8E79, 0x00000000],
[A6XXRegs.REG_A7XX_RB_UNKNOWN_8899, 0x00000000],
[A6XXRegs.REG_A7XX_RB_LRZ_CNTL2, 0x00000000],
[A6XXRegs.REG_A7XX_RB_CCU_DBG_ECO_CNTL, 0x02080000],
[A6XXRegs.REG_A6XX_VPC_DBG_ECO_CNTL, 0x02000000],
[A6XXRegs.REG_A6XX_UCHE_UNKNOWN_0E12, 0x3200000],
@ -1112,7 +1112,7 @@ a740_raw_magic_regs = [
[A6XXRegs.REG_A6XX_GRAS_DBG_ECO_CNTL, 0x00004800],
[A6XXRegs.REG_A7XX_RB_UNKNOWN_8E79, 0x00000000],
[A6XXRegs.REG_A7XX_RB_UNKNOWN_8899, 0x00000000],
[A6XXRegs.REG_A7XX_RB_LRZ_CNTL2, 0x00000000],
[A6XXRegs.REG_A7XX_RB_UNKNOWN_8C34, 0x00000000],
[A6XXRegs.REG_A7XX_RB_CCU_DBG_ECO_CNTL, 0x02080000],
[A6XXRegs.REG_A6XX_VPC_DBG_ECO_CNTL, 0x02000000],
@ -1212,7 +1212,7 @@ add_gpus([
[A6XXRegs.REG_A6XX_GRAS_DBG_ECO_CNTL, 0x00004800],
[A6XXRegs.REG_A7XX_RB_UNKNOWN_8E79, 0x00000000],
[A6XXRegs.REG_A7XX_RB_UNKNOWN_8899, 0x00000000],
[A6XXRegs.REG_A7XX_RB_LRZ_CNTL2, 0x00000000],
[A6XXRegs.REG_A7XX_RB_UNKNOWN_8C34, 0x00000000],
[A6XXRegs.REG_A7XX_RB_CCU_DBG_ECO_CNTL, 0x02080000],
[A6XXRegs.REG_A6XX_VPC_DBG_ECO_CNTL, 0x02000000],
@ -1295,7 +1295,7 @@ add_gpus([
[A6XXRegs.REG_A6XX_GRAS_DBG_ECO_CNTL, 0x00004800],
[A6XXRegs.REG_A7XX_RB_UNKNOWN_8E79, 0x00000000],
[A6XXRegs.REG_A7XX_RB_UNKNOWN_8899, 0x00000000],
[A6XXRegs.REG_A7XX_RB_LRZ_CNTL2, 0x00000000],
[A6XXRegs.REG_A7XX_RB_CCU_DBG_ECO_CNTL, 0x02080000],
[A6XXRegs.REG_A6XX_VPC_DBG_ECO_CNTL, 0x02000000],
[A6XXRegs.REG_A6XX_UCHE_UNKNOWN_0E12, 0],
@ -1375,7 +1375,7 @@ add_gpus([
[A6XXRegs.REG_A7XX_GRAS_ROTATION_CNTL, 0x00000000],
[A6XXRegs.REG_A6XX_GRAS_DBG_ECO_CNTL, 0x00004800],
[A6XXRegs.REG_A7XX_RB_UNKNOWN_8899, 0x00000000],
[A6XXRegs.REG_A7XX_RB_LRZ_CNTL2, 0x00000000],
[A6XXRegs.REG_A7XX_RB_UNKNOWN_8C34, 0x00000000],
[A6XXRegs.REG_A7XX_RB_CCU_DBG_ECO_CNTL, 0x02082000],

4
src/freedreno/registers/adreno/a6xx.xml
View file

@ -2454,7 +2454,9 @@ by a particular renderpass/blit.
<reg32 offset="0x8898" name="RB_LRZ_CNTL" usage="rp_blit">
<bitfield name="ENABLE" pos="0" type="boolean"/>
</reg32>
<reg32 offset="0x8899" name="RB_UNKNOWN_8899" variants="A7XX-" usage="cmd"/>
<reg32 offset="0x8899" name="RB_LRZ_CNTL2" variants="A7XX-" usage="cmd">
<bitfield name="ENABLE_BIDIRECTIONAL_LRZ" pos="0" type="boolean"/>
</reg32>
<!-- 0x8899-0x88bf invalid -->
<!-- clamps depth value for depth test/write -->
<reg32 offset="0x88c0" name="RB_VIEWPORT_ZCLAMP_MIN" type="float" usage="rp_blit" variants="A6XX-A7XX"/>