There's a recently discovered HW bug affecting hardware at least as far
back as Skylake where, if the LOD is out-of-bounds for any SIMD lane,
then garbage may be returned in all SIMD lanes. The easy solution is to
set lower_txs_lod so that we always have a constant LOD of 0 which we
know a priori is always in-bounds. Fortunately, not many shaders
actually use textureSize() with LOD.
Shader-db results on Ice Lake:
total instructions in shared programs: 19948537 -> 19948564 (<.01%)
instructions in affected programs: 3859 -> 3886 (0.70%)
helped: 0
HURT: 7
One of the shaders is in Civilization: Beyond Earth, and the rest are
all in Civilization VI.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10538>
(cherry picked from commit 05a37e2422)
a0.x is written as a half-reg, but just interpreting it as "hr61.x" will
result in it overlapping with r30.z in merged mode, which is not what
the hardware does at all. This introduced a spurious dependency on
a write to r30.z which resulted in an assert tripping. Just pretend it's
a full reg instead.
This fixes
spec@arb_tessellation_shader@execution@variable-indexing@vs-output-array-vec3-index-wr-before-tcs
with the new RA.
Fixes: 0f78c32 ("freedreno/ir3: post-RA sched pass")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10591>
(cherry picked from commit e597f8b122)
If the secondary has a list of CS buffers, it should be copied to
the primary.
Fixes dEQP-VK.api.command_buffers.record_many_draws_secondary_2.
Cc: 21.1 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10547>
(cherry picked from commit 12a00da800)
Fixes an assertion triggered by new CTS:
dEQP-VK.renderpass2.suballocation.multisample_resolve.*_resolve_level_*
Looks like the driver should pass a range to radv_layout_dcc_compressed().
Cc: 21.1 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10502>
(cherry picked from commit 80f55e5163)
Since commit f39fd3dce7 a new GLX error is issued in case context creation
fails. This broke wine on certain hardware: While wine installs an error handler
to ignore this kind of error, it does not function because it expects the
dpy->request serial number of the error to be incremented since the installation
of the handler.
Workaround this by artificially increasing the request number. This also
guarantees a unique serial number for the error.
Fixes: f39fd3dce7
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3969
Signed-off-by: Bastian Beranek <bastian.beischer@rwth-aachen.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10565>
(cherry picked from commit 960c86d678)
The max values are inclusive, so add 1 before aligning. This means
that a max of 32 will be aligned up to 64 then be decremented to 63.
Add a comment to the pan_fb_info struct to document maxx and maxy as
inclusive.
Fixes: 8ba2f9f698 ("panfrost: Create a blitter library to replace the existing preload helpers")
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10542>
(cherry picked from commit ab8e531cf0)
The prototype uses a pointer and the actual function definition had an
array. For some reason, GCC never complained about this until GCC 11.
This fixes a compile warning when building with GCC 11.
Fixes: 09ced65420 "intel/isl: Add format conversion code"
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10537>
(cherry picked from commit b80720acb1)
With the missing else, this prints the compacted hex followed by hex
for an uncompacted version of the compacted instruction. It also
doesn't print hex for instructions that are not compacted.
Fixes: bc4a127d6e ("intel/disasm: Label support in shader disassembly for UIP/JIP")
Fixes: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4245
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10535>
(cherry picked from commit 3f04383521)
For non 64bit devices the key stored in hash_table_u64 is wrapped in
hash_key_u64 structure, which is never free.
This commit fixes this issue by just removing the user-defined
`delete_function` parameter in hash_table_u64_{destroy,clear} (which
nobody is using) and using instead a delete function to free this
structure.
Fixes: 608257cf82 ("i965: Fix INTEL_DEBUG=bat")
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10480>
(cherry picked from commit e532a47f76)
Conflicts:
src/microsoft/compiler/dxil_nir.c
If radv_pipeline_cache_insert_shaders() finds a GS copy shader in the
cache, it will free the variant in gs_variants and replace it with the one
in the cache.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10433>
(cherry picked from commit d6894b643b)
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Fixes: bd1705a480 ("vulkan: Make vk_debug_report_callback derive from vk_object_base")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10433>
(cherry picked from commit 32ebbd8c23)
The idea behind this assert is that if a buffer is in
bufmgr->handle_table it's because it has been shared from i965 to the
outside. This is when we add the drm FD associated to this BO to
bo->exports.
But we also import buffer from the outside into i965 and those buffers
don't have an associated drm FD added to bo->exports.
If you import the same buffer more than once, you'll run into this
assert.
v2: Also drop assert from brw_bo_gem_create_from_name() (Ian)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 57e4d0aa1c ("i965: fix export of GEM handles")
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10386>
(cherry picked from commit 03e97e94e7)
I mixed up the EXT and ARB version of the extensions; we actually do
require shaderStorageImageWriteWithoutFormat as well here.
Thanks to Ilia Mirkin for pointing this out.
It also seems I got really confused about what was required when writing
the docs, so let's fix that as well.
Fixes: 341332b23a ("zink: correct image cap checks")
Fixes: ecac7f3da1 ("docs: add missing zink-requirement")
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10463>
(cherry picked from commit 4ec8533f69)
Conflicts:
docs/drivers/zink.rst
This fixes a bunch of MSAA related CTS regressions. This restores
previous behaviour on GFX9 but it should be fixed properly.
Cc: 21.1 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10374>
(cherry picked from commit a854a9fa62)
$(MESA_TOP)/src/compiler/nir include path is added
for both clarity and build errors preventive reasons
Cc: 21.0 21.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10443>
(cherry picked from commit a02328395d)
Since generated nir headers are included, it makes sense to include nir path
Fixes the following building error:
FAILED: out/target/product/x86_64/obj/STATIC_LIBRARIES/libmesa_pipe_radeonsi_intermediates/si_shader_nir.o
...
In file included from external/mesa/src/gallium/drivers/radeonsi/si_shader_nir.c:26:
external/mesa/src/amd/common/ac_nir.h:29:10: fatal error: 'nir.h' file not found
^~~~~~~
1 error generated.
Cc: 21.0 21.1 <mesa-stable@lists.freedesktop.org>
Fixes: 1c702a8239 ("ac: move ac_lower_indirect_derefs() outside of the LLVM dir")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10443>
(cherry picked from commit e213bfd330)
Don't setup inputs and outputs if we aren't using
load_input/store_output intrinsics. While it's mostly harmless, there
may be more outputs than expected which would lead to an oob write of
the outputs array when setting the register id to INVALID_REG.
Also be more paranoid with asserts to catch this.
Fixes: a6291b1 ("freedreno/ir3: rework setup_{input,output} to make struct varyings work")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7274>
(cherry picked from commit decfea2f4e)
This makes the vertex order of TRISTRIP and TRISTRIP_ADJ primitves
consistent between XFB output and GS input. Technically, the Vulkan
spec allows us to XFB out in whatever order we want but being consistent
with GS inputs is probably nicer to apps.
Fixes: 36ee2fd61c "anv: Implement the basic form of VK_EXT_transform_feedback"
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10460>
(cherry picked from commit 22b8bcda2c)
PIPE_CAP_IMAGE_LOAD_FORMATTED doesn't depend on
shaderStorageImageExtendedFormats or
shaderStorageImageWriteWithoutFormat.
PIPE_SHADER_CAP_MAX_SHADER_IMAGES enables
GL_EXT_shader_image_load_store, which *does* require
shaderStorageImageExtendedFormats. Having
shaderStorageImageWriteWithoutFormat and
shaderStorageImageReadWithoutFormat isn't enough to support this.
It *might* be possible to lower extended formats to format-less
reads or writes, but we don't currently do that, so we should
just correct the test for now.
Fixes: 3f9a6d333b ("zink: export shader image caps using features")
Fixes: 5282210c0b ("zink: check correct caps for PIPE_CAP_IMAGE_LOAD_FORMATTED")
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10456>
(cherry picked from commit 341332b23a)
The claim that we require vulkan memory model's MakeAvailable and
MakeVisible semantics for image writes isn't accurate. This would be
required *if* we were already using the Vulkan memory model.
But we're using the GLSL450 memory model in those cases, which has no
such requirements.
This means that any problems on RADV due to the lack of these semantics
are RADV bugs, and should be fixed in RADV instead.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10345>
(cherry picked from commit 95d9d811c9)
