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pan/mdg: Fix calculation of available work registers

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Make the rmu variable signed; otherwise the MAX2 has no effect and
work_count can end up being larger than 16.

Fixes INSTR_OPERAND_FAULTs in SuperTuxKart.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4707
Fixes: c6ed8bf77c ("panfrost: Fix uniform_count on Midgard")
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10507>
This commit is contained in:
Icecream95 2021-04-29 11:27:28 +12:00 • committed by Marge Bot
parent 3f04383521
commit f85b7aa5d4
1 changed files with 1 additions and 1 deletions
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src/panfrost/midgard/midgard_ra.c
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@ -394,7 +394,7 @@ allocate_registers(compiler_context *ctx, bool *spilled)
/* The number of vec4 work registers available depends on the number of
* register-mapped uniforms and the shader stage. By ABI we limit blend
* shaders to 8 registers, should be lower XXX */
unsigned rmu = ctx->info->push.count / 4;
int rmu = ctx->info->push.count / 4;
int work_count = ctx->inputs->is_blend ? 8 : 16 - MAX2(rmu - 8, 0);
/* No register allocation to do with no SSA */