ir3/postsched: Fix dependencies for a0.x/p0.x

a0.x is written as a half-reg, but just interpreting it as "hr61.x" will
result in it overlapping with r30.z in merged mode, which is not what
the hardware does at all. This introduced a spurious dependency on
a write to r30.z which resulted in an assert tripping. Just pretend it's
a full reg instead.

This fixes
spec@arb_tessellation_shader@execution@variable-indexing@vs-output-array-vec3-index-wr-before-tcs
with the new RA.

Fixes: 0f78c32 ("freedreno/ir3: post-RA sched pass")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10591>
(cherry picked from commit e597f8b122)

.pick_status.json

@@ -553,7 +553,7 @@
         "description": "ir3/postsched: Fix dependencies for a0.x/p0.x",
         "nominated": true,
         "nomination_type": 1,
-        "resolution": 0,
+        "resolution": 1,
         "master_sha": null,
         "because_sha": "0f78c32492ed096649b015a4967d6d56c18dd14a"
     },

src/freedreno/ir3/ir3_postsched.c

@@ -380,7 +380,11 @@ add_reg_dep(struct ir3_postsched_deps_state *state,
 		unsigned num, bool write)
 {
 	if (state->merged) {
-		if (reg->flags & IR3_REG_HALF) {
+		/* Make sure that special registers like a0.x that are written as
+		 * half-registers don't alias random full registers by pretending that
+		 * they're full registers:
+		 */
+		if ((reg->flags & IR3_REG_HALF) && num < regid(48, 0)) {
 			/* single conflict in half-reg space: */
 			add_single_reg_dep(state, node, num, write);
 		} else {