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pan/mdg: Fix calculation of available work registers

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Make the rmu variable signed; otherwise the MAX2 has no effect and
work_count can end up being larger than 16.

Fixes INSTR_OPERAND_FAULTs in SuperTuxKart.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4707
Fixes: c6ed8bf77c ("panfrost: Fix uniform_count on Midgard")
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10507>
(cherry picked from commit f85b7aa5d4)
This commit is contained in:
Icecream95 2021-04-29 11:27:28 +12:00 • committed by Dylan Baker
parent baaf7cfb82
commit 4c0b3b5d9e
2 changed files with 2 additions and 2 deletions
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2
.pick_status.json
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@ -130,7 +130,7 @@
"description": "pan/mdg: Fix calculation of available work registers",
"nominated": true,
"nomination_type": 1,
"resolution": 0,
"resolution": 1,
"master_sha": null,
"because_sha": "c6ed8bf77cb8b78f98ff4924816ee052a9aa2c7b"
},

2
src/panfrost/midgard/midgard_ra.c
View file

@ -394,7 +394,7 @@ allocate_registers(compiler_context *ctx, bool *spilled)
/* The number of vec4 work registers available depends on the number of
* register-mapped uniforms and the shader stage. By ABI we limit blend
* shaders to 8 registers, should be lower XXX */
unsigned rmu = ctx->info->push.count / 4;
int rmu = ctx->info->push.count / 4;
int work_count = ctx->inputs->is_blend ? 8 : 16 - MAX2(rmu - 8, 0);
/* No register allocation to do with no SSA */