fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-07 04:58:05 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 4

util: fix (re-enable) L3 cache pinning

Browse source 
cores_per_L3 was uninitialized, so it was always disabled.
Remove the variable and do it differently.

Fixes: 11d2db17c5 - util: rework AMD cpu L3 cache affinity code.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10526>
(cherry picked from commit 48d2ac4e88)
This commit is contained in:
Marek Olšák 2021-04-28 21:27:02 -04:00 • committed by Eric Engestrom
parent 8f8ce535ef
commit 3707ffe7bc
5 changed files with 5 additions and 5 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
.pick_status.json
View file

@ -166,7 +166,7 @@
"description": "util: fix (re-enable) L3 cache pinning",
"nominated": true,
"nomination_type": 1,
"resolution": 0,
"resolution": 1,
"master_sha": null,
"because_sha": "11d2db17c522e5a123e781f001d7f75e9abe2bcd"
},

2
src/mesa/main/glthread.c
View file

@ -216,7 +216,7 @@ _mesa_glthread_flush_batch(struct gl_context *ctx)
/* Pin threads regularly to the same Zen CCX that the main thread is
* running on. The main thread can move between CCXs.
*/
if (util_get_cpu_caps()->nr_cpus != util_get_cpu_caps()->cores_per_L3 &&
if (util_get_cpu_caps()->num_L3_caches > 1 &&
/* driver support */
ctx->Driver.PinDriverToL3Cache &&
++glthread->pin_thread_counter % 128 == 0) {

4
src/mesa/state_tracker/st_context.c
View file

@ -843,7 +843,9 @@ st_create_context_priv(struct gl_context *ctx, struct pipe_context *pipe,
!st->lower_ucp;
st->shader_has_one_variant[MESA_SHADER_COMPUTE] = st->has_shareable_shaders;
if (util_get_cpu_caps()->cores_per_L3 == util_get_cpu_caps()->nr_cpus ||
util_cpu_detect();
if (util_get_cpu_caps()->num_L3_caches == 1 ||
!st->pipe->set_context_param)
st->pin_thread_counter = ST_L3_PINNING_DISABLED;

1
src/util/u_cpu_detect.c
View file

@ -435,7 +435,6 @@ static void
get_cpu_topology(void)
{
/* Default. This is OK if L3 is not present or there is only one. */
util_cpu_caps.cores_per_L3 = util_cpu_caps.nr_cpus;
util_cpu_caps.num_L3_caches = 1;
memset(util_cpu_caps.cpu_to_L3, 0xff, sizeof(util_cpu_caps.cpu_to_L3));

1
src/util/u_cpu_detect.h
View file

@ -97,7 +97,6 @@ struct util_cpu_caps_t {
unsigned has_avx512vbmi:1;
unsigned num_L3_caches;
unsigned cores_per_L3;
unsigned num_cpu_mask_bits;
uint16_t cpu_to_L3[UTIL_MAX_CPUS];