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radv,aco: use nir_address_format_vec2_index_32bit_offset
The vec2 index helps the compiler make use of SMEM's SOFFSET field when loading descriptors. fossil-db (GFX10.3): Totals from 126326 (86.37% of 146267) affected shaders: VGPRs: 4898704 -> 4899088 (+0.01%); split: -0.02%, +0.03% SpillSGPRs: 13490 -> 14404 (+6.78%); split: -1.10%, +7.87% CodeSize: 306442996 -> 302277700 (-1.36%); split: -1.36%, +0.01% MaxWaves: 3277108 -> 3276624 (-0.01%); split: +0.01%, -0.02% Instrs: 58301101 -> 57469370 (-1.43%); split: -1.43%, +0.01% VClause: 1208270 -> 1199264 (-0.75%); split: -1.02%, +0.28% SClause: 2517691 -> 2432744 (-3.37%); split: -3.75%, +0.38% Copies: 3518643 -> 3161097 (-10.16%); split: -10.45%, +0.29% Branches: 1228383 -> 1228254 (-0.01%); split: -0.12%, +0.11% PreSGPRs: 3973880 -> 4031099 (+1.44%); split: -0.19%, +1.63% PreVGPRs: 3831599 -> 3831707 (+0.00%) Cycles: 1785250712 -> 1778222316 (-0.39%); split: -0.42%, +0.03% VMEM: 52873776 -> 50663317 (-4.18%); split: +0.18%, -4.36% SMEM: 8534270 -> 8361666 (-2.02%); split: +1.79%, -3.82% Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9523>
This commit is contained in:
Rhys Perry
Marge Bot
parent
7a7838529a
commit
ee9b744cb5
7 changed files with 98 additions and 76 deletions
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@ -4998,46 +4998,29 @@ void visit_load_resource(isel_context *ctx, nir_intrinsic_instr *instr)
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stride = layout->binding[binding].size;
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}
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nir_const_value* nir_const_index = nir_src_as_const_value(instr->src[0]);
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unsigned const_index = nir_const_index ? nir_const_index->u32 : 0;
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if (stride != 1) {
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if (nir_const_index) {
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const_index = const_index * stride;
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} else if (index.type() == RegType::vgpr) {
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if (nir_src_is_const(instr->src[0])) {
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index = bld.copy(bld.def(s1), Operand((uint32_t)(offset + nir_src_as_uint(instr->src[0]) * stride)));
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} else if (index.type() == RegType::vgpr) {
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if (stride != 1) {
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bool index24bit = layout->binding[binding].array_size <= 0x1000000;
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index = bld.v_mul_imm(bld.def(v1), index, stride, index24bit);
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} else {
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index = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(stride), Operand(index));
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}
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}
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if (offset) {
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if (nir_const_index) {
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const_index = const_index + offset;
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} else if (index.type() == RegType::vgpr) {
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if (offset)
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index = bld.vadd32(bld.def(v1), Operand(offset), index);
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} else {
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index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), Operand(offset), Operand(index));
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}
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}
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if (nir_const_index && const_index == 0) {
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index = desc_ptr;
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} else if (index.type() == RegType::vgpr) {
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index = bld.vadd32(bld.def(v1),
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nir_const_index ? Operand(const_index) : Operand(index),
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Operand(desc_ptr));
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} else {
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index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc),
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nir_const_index ? Operand(const_index) : Operand(index),
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Operand(desc_ptr));
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if (stride != 1)
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index = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(stride), index);
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if (offset)
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index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), Operand(offset), index);
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}
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Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
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std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
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elems[0] = index;
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elems[0] = desc_ptr;
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elems[1] = index;
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ctx->allocated_vec.emplace(dst.id(), elems);
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bld.pseudo(aco_opcode::p_create_vector, Definition(dst), index,
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Operand((unsigned)ctx->options->address32_hi));
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bld.pseudo(aco_opcode::p_create_vector, Definition(dst), desc_ptr, index,
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Operand(0u));
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}
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void load_buffer(isel_context *ctx, unsigned num_components, unsigned component_size,
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@ -5061,6 +5044,25 @@ void load_buffer(isel_context *ctx, unsigned num_components, unsigned component_
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emit_load(ctx, bld, info, mubuf_load_params);
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}
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Temp load_buffer_rsrc(isel_context *ctx, Temp rsrc)
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{
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Builder bld(ctx->program, ctx->block);
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Temp set_ptr = emit_extract_vector(ctx, rsrc, 0, RegClass(rsrc.type(), 1));
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Temp binding = bld.as_uniform(emit_extract_vector(ctx, rsrc, 1, RegClass(rsrc.type(), 1)));
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set_ptr = convert_pointer_to_64_bit(ctx, set_ptr);
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return bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), set_ptr, binding);
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}
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bool is_inline_ubo(isel_context *ctx, nir_src rsrc)
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{
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nir_binding binding = nir_chase_binding(rsrc);
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if (!binding.success)
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return false;
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radv_descriptor_set_layout *layout = ctx->options->layout->set[binding.desc_set].layout;
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return layout->binding[binding.binding].type == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT;
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}
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void visit_load_ubo(isel_context *ctx, nir_intrinsic_instr *instr)
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{
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Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
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@ -5068,11 +5070,11 @@ void visit_load_ubo(isel_context *ctx, nir_intrinsic_instr *instr)
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Builder bld(ctx->program, ctx->block);
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nir_binding binding = nir_chase_binding(instr->src[0]);
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assert(binding.success);
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radv_descriptor_set_layout *layout = ctx->options->layout->set[binding.desc_set].layout;
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if (is_inline_ubo(ctx, instr->src[0])) {
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Temp set_ptr = bld.as_uniform(emit_extract_vector(ctx, rsrc, 0, RegClass(rsrc.type(), 1)));
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Temp binding_off = bld.as_uniform(emit_extract_vector(ctx, rsrc, 1, RegClass(rsrc.type(), 1)));
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rsrc = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), set_ptr, binding_off);
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if (layout->binding[binding.binding].type == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT) {
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uint32_t desc_type = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
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S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
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S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
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@ -5085,15 +5087,11 @@ void visit_load_ubo(isel_context *ctx, nir_intrinsic_instr *instr)
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desc_type |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
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S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
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}
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Temp upper_dwords = bld.pseudo(aco_opcode::p_create_vector, bld.def(s3),
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Operand(S_008F04_BASE_ADDRESS_HI(ctx->options->address32_hi)),
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Operand(0xFFFFFFFFu),
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Operand(desc_type));
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rsrc = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
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rsrc, upper_dwords);
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rsrc = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4), rsrc,
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Operand(S_008F04_BASE_ADDRESS_HI(ctx->options->address32_hi)),
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Operand(0xFFFFFFFFu), Operand(desc_type));
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} else {
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rsrc = convert_pointer_to_64_bit(ctx, rsrc);
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rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
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rsrc = load_buffer_rsrc(ctx, rsrc);
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}
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unsigned size = instr->dest.ssa.bit_size / 8;
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load_buffer(ctx, instr->num_components, size, dst, rsrc, get_ssa_temp(ctx, instr->src[1].ssa),
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@ -6190,8 +6188,7 @@ void visit_load_ssbo(isel_context *ctx, nir_intrinsic_instr *instr)
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unsigned num_components = instr->num_components;
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Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
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Temp rsrc = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
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rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
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Temp rsrc = load_buffer_rsrc(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
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unsigned access = nir_intrinsic_access(instr);
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bool glc = access & (ACCESS_VOLATILE | ACCESS_COHERENT);
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@ -6217,8 +6214,7 @@ void visit_store_ssbo(isel_context *ctx, nir_intrinsic_instr *instr)
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unsigned writemask = widen_mask(nir_intrinsic_write_mask(instr), elem_size_bytes);
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Temp offset = get_ssa_temp(ctx, instr->src[2].ssa);
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Temp rsrc = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
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rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
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Temp rsrc = load_buffer_rsrc(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
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memory_sync_info sync = get_memory_sync_info(instr, storage_buffer, 0);
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bool glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE);
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@ -6269,8 +6265,7 @@ void visit_atomic_ssbo(isel_context *ctx, nir_intrinsic_instr *instr)
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get_ssa_temp(ctx, instr->src[3].ssa), data);
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Temp offset = get_ssa_temp(ctx, instr->src[1].ssa);
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Temp rsrc = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
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rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
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Temp rsrc = load_buffer_rsrc(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
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Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
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@ -6342,17 +6337,20 @@ void visit_get_ssbo_size(isel_context *ctx, nir_intrinsic_instr *instr) {
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Temp rsrc = get_ssa_temp(ctx, instr->src[0].ssa);
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Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
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bool non_uniform = dst.type() == RegType::vgpr;
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Temp index = convert_pointer_to_64_bit(ctx, rsrc, non_uniform);
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Builder bld(ctx->program, ctx->block);
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if (non_uniform) {
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Temp set_ptr = emit_extract_vector(ctx, rsrc, 0, RegClass(rsrc.type(), 1));
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Temp binding = emit_extract_vector(ctx, rsrc, 1, RegClass(rsrc.type(), 1));
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Temp index = bld.vadd32(bld.def(v1), set_ptr, binding);
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index = convert_pointer_to_64_bit(ctx, index, non_uniform);
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LoadEmitInfo info = {Operand(index), dst, 1, 4};
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info.align_mul = 4;
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info.const_offset = 8;
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emit_load(ctx, bld, info, global_load_params);
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} else {
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Temp desc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), index, Operand(0u));
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emit_extract_vector(ctx, desc, 2, dst);
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emit_extract_vector(ctx, load_buffer_rsrc(ctx, rsrc), 2, dst);
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}
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}
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@ -145,7 +145,7 @@ BEGIN_TEST(isel.sparse.clause)
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QO_EXTENSION GL_ARB_sparse_texture2 : require
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layout(local_size_x=1) in;
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layout(binding=0) uniform sampler2D tex;
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layout(binding=0) buffer Buf {
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layout(binding=1) buffer Buf {
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vec4 res[4];
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uint code[4];
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};
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@ -492,15 +492,20 @@ static LLVMValueRef enter_waterfall(struct ac_nir_context *ctx, struct waterfall
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ac_build_bgnloop(&ctx->ac, 6000);
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LLVMValueRef scalar_value = ac_build_readlane(&ctx->ac, value, NULL);
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LLVMValueRef active = LLVMConstInt(ctx->ac.i1, 1, false);
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LLVMValueRef scalar_value[NIR_MAX_VEC_COMPONENTS];
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LLVMValueRef active =
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LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, value, scalar_value, "uniform_active");
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for (unsigned i = 0; i < ac_get_llvm_num_components(value); i++) {
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LLVMValueRef comp = ac_llvm_extract_elem(&ctx->ac, value, i);
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scalar_value[i] = ac_build_readlane(&ctx->ac, comp, NULL);
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active = LLVMBuildAnd(ctx->ac.builder, active,
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LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, comp, scalar_value[i], ""), "");
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}
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wctx->phi_bb[0] = LLVMGetInsertBlock(ctx->ac.builder);
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ac_build_ifcc(&ctx->ac, active, 6001);
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return scalar_value;
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return ac_build_gather_values(&ctx->ac, scalar_value, ac_get_llvm_num_components(value));
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}
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static LLVMValueRef exit_waterfall(struct ac_nir_context *ctx, struct waterfall_context *wctx,
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@ -653,7 +653,7 @@ radv_meta_build_resolve_shader_core(nir_builder *b, bool is_integer, int samples
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nir_ssa_def *
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radv_meta_load_descriptor(nir_builder *b, unsigned desc_set, unsigned binding)
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{
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nir_ssa_def *rsrc = nir_vulkan_resource_index(b, 2, 32, nir_imm_int(b, 0), .desc_set = desc_set,
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nir_ssa_def *rsrc = nir_vulkan_resource_index(b, 3, 32, nir_imm_int(b, 0), .desc_set = desc_set,
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.binding = binding);
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return nir_channel(b, rsrc, 0);
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return nir_channels(b, rsrc, 0x3);
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}
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@ -223,11 +223,10 @@ radv_load_resource(struct ac_shader_abi *abi, LLVMValueRef index, unsigned desc_
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offset = ac_build_imad(&ctx->ac, index, stride, offset);
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}
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desc_ptr = LLVMBuildGEP(ctx->ac.builder, desc_ptr, &offset, 1, "");
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desc_ptr = LLVMBuildPtrToInt(ctx->ac.builder, desc_ptr, ctx->ac.i32, "");
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LLVMValueRef res[] = {desc_ptr, ctx->ac.i32_0};
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return ac_build_gather_values(&ctx->ac, res, 2);
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LLVMValueRef res[] = {desc_ptr, offset, ctx->ac.i32_0};
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return ac_build_gather_values(&ctx->ac, res, 3);
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}
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static uint32_t
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@ -416,8 +415,12 @@ radv_load_base_vertex(struct ac_shader_abi *abi, bool non_indexed_is_zero)
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}
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static LLVMValueRef
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convert_pointer_to_64_bit(struct radv_shader_context *ctx, LLVMValueRef ptr, bool non_uniform)
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get_desc_ptr(struct radv_shader_context *ctx, LLVMValueRef ptr, bool non_uniform)
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{
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LLVMValueRef set_ptr = ac_llvm_extract_elem(&ctx->ac, ptr, 0);
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LLVMValueRef offset = ac_llvm_extract_elem(&ctx->ac, ptr, 1);
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ptr = LLVMBuildNUWAdd(ctx->ac.builder, set_ptr, offset, "");
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unsigned addr_space = AC_ADDR_SPACE_CONST_32BIT;
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if (non_uniform) {
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/* 32-bit seems to always use SMEM. addrspacecast from 32-bit -> 64-bit is broken. */
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@ -436,7 +439,7 @@ radv_load_ssbo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr, bool write, b
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struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
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LLVMValueRef result;
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buffer_ptr = convert_pointer_to_64_bit(ctx, buffer_ptr, non_uniform);
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buffer_ptr = get_desc_ptr(ctx, buffer_ptr, non_uniform);
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if (!non_uniform)
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LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
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@ -458,6 +461,10 @@ radv_load_ubo(struct ac_shader_abi *abi, unsigned desc_set, unsigned binding, bo
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struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
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if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT) {
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LLVMValueRef set_ptr = ac_llvm_extract_elem(&ctx->ac, buffer_ptr, 0);
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LLVMValueRef offset = ac_llvm_extract_elem(&ctx->ac, buffer_ptr, 1);
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buffer_ptr = LLVMBuildNUWAdd(ctx->ac.builder, set_ptr, offset, "");
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uint32_t desc_type =
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S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) | S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
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S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
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@ -482,7 +489,7 @@ radv_load_ubo(struct ac_shader_abi *abi, unsigned desc_set, unsigned binding, bo
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}
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}
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buffer_ptr = convert_pointer_to_64_bit(ctx, buffer_ptr, false);
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buffer_ptr = get_desc_ptr(ctx, buffer_ptr, false);
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LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
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result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
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@ -3174,6 +3174,14 @@ opt_vectorize_callback(const nir_instr *instr, void *_)
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}
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}
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static nir_component_mask_t
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non_uniform_access_callback(const nir_src *src, void *_)
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{
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if (src->ssa->num_components == 1)
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return 0x1;
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return nir_chase_binding(*src).success ? 0x2 : 0x3;
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}
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VkResult
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radv_create_shaders(struct radv_pipeline *pipeline, struct radv_device *device,
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struct radv_pipeline_cache *cache, const struct radv_pipeline_key *pipeline_key,
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@ -3305,7 +3313,8 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_device *device,
|
|||
nir_lower_non_uniform_access_options options = {
|
||||
.types = nir_lower_non_uniform_ubo_access | nir_lower_non_uniform_ssbo_access |
|
||||
nir_lower_non_uniform_texture_access | nir_lower_non_uniform_image_access,
|
||||
.callback = NULL,
|
||||
.callback = &non_uniform_access_callback,
|
||||
.callback_data = NULL,
|
||||
};
|
||||
NIR_PASS_V(nir[i], nir_lower_non_uniform_access, &options);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -285,16 +285,18 @@ lower_intrinsics(nir_shader *nir, const struct radv_pipeline_key *key,
|
|||
|
||||
nir_ssa_def *def = NULL;
|
||||
if (intrin->intrinsic == nir_intrinsic_load_vulkan_descriptor) {
|
||||
def = nir_vec2(&b, nir_channel(&b, intrin->src[0].ssa, 0), nir_imm_int(&b, 0));
|
||||
def = nir_vec3(&b, nir_channel(&b, intrin->src[0].ssa, 0),
|
||||
nir_channel(&b, intrin->src[0].ssa, 1), nir_imm_int(&b, 0));
|
||||
} else if (intrin->intrinsic == nir_intrinsic_vulkan_resource_index) {
|
||||
unsigned desc_set = nir_intrinsic_desc_set(intrin);
|
||||
unsigned binding = nir_intrinsic_binding(intrin);
|
||||
struct radv_descriptor_set_layout *desc_layout = layout->set[desc_set].layout;
|
||||
|
||||
nir_ssa_def *new_res = nir_vulkan_resource_index(
|
||||
&b, 2, 32, intrin->src[0].ssa, .desc_set = desc_set, .binding = binding,
|
||||
&b, 3, 32, intrin->src[0].ssa, .desc_set = desc_set, .binding = binding,
|
||||
.desc_type = nir_intrinsic_desc_type(intrin));
|
||||
nir_ssa_def *ptr = nir_channel(&b, new_res, 0);
|
||||
nir_ssa_def *set_ptr = nir_channel(&b, new_res, 0);
|
||||
nir_ssa_def *binding_ptr = nir_channel(&b, new_res, 1);
|
||||
|
||||
nir_ssa_def *stride;
|
||||
if (desc_layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
|
||||
|
|
@ -303,12 +305,13 @@ lower_intrinsics(nir_shader *nir, const struct radv_pipeline_key *key,
|
|||
} else {
|
||||
stride = nir_imm_int(&b, desc_layout->binding[binding].size);
|
||||
}
|
||||
def = nir_vec2(&b, ptr, stride);
|
||||
def = nir_vec3(&b, set_ptr, binding_ptr, stride);
|
||||
} else if (intrin->intrinsic == nir_intrinsic_vulkan_resource_reindex) {
|
||||
nir_ssa_def *ptr = nir_channel(&b, intrin->src[0].ssa, 0);
|
||||
nir_ssa_def *stride = nir_channel(&b, intrin->src[0].ssa, 1);
|
||||
ptr = nir_iadd(&b, ptr, nir_imul(&b, intrin->src[1].ssa, stride));
|
||||
def = nir_vec2(&b, ptr, stride);
|
||||
nir_ssa_def *set_ptr = nir_channel(&b, intrin->src[0].ssa, 0);
|
||||
nir_ssa_def *binding_ptr = nir_channel(&b, intrin->src[0].ssa, 1);
|
||||
nir_ssa_def *stride = nir_channel(&b, intrin->src[0].ssa, 2);
|
||||
binding_ptr = nir_iadd(&b, binding_ptr, nir_imul(&b, intrin->src[1].ssa, stride));
|
||||
def = nir_vec3(&b, set_ptr, binding_ptr, stride);
|
||||
} else if (intrin->intrinsic == nir_intrinsic_is_sparse_texels_resident) {
|
||||
def = nir_ieq_imm(&b, intrin->src[0].ssa, 0);
|
||||
} else if (intrin->intrinsic == nir_intrinsic_sparse_residency_code_and) {
|
||||
|
|
@ -457,8 +460,8 @@ radv_shader_compile_to_nir(struct radv_device *device, struct vk_shader_module *
|
|||
.fragment_shading_rate = device->physical_device->rad_info.chip_class >= GFX10_3,
|
||||
.workgroup_memory_explicit_layout = true,
|
||||
},
|
||||
.ubo_addr_format = nir_address_format_32bit_index_offset,
|
||||
.ssbo_addr_format = nir_address_format_32bit_index_offset,
|
||||
.ubo_addr_format = nir_address_format_vec2_index_32bit_offset,
|
||||
.ssbo_addr_format = nir_address_format_vec2_index_32bit_offset,
|
||||
.phys_ssbo_addr_format = nir_address_format_64bit_global,
|
||||
.push_const_addr_format = nir_address_format_logical,
|
||||
.shared_addr_format = nir_address_format_32bit_offset,
|
||||
|
|
@ -636,7 +639,7 @@ radv_shader_compile_to_nir(struct radv_device *device, struct vk_shader_module *
|
|||
NIR_PASS_V(nir, nir_lower_explicit_io, nir_var_mem_push_const, nir_address_format_32bit_offset);
|
||||
|
||||
NIR_PASS_V(nir, nir_lower_explicit_io, nir_var_mem_ubo | nir_var_mem_ssbo,
|
||||
nir_address_format_32bit_index_offset);
|
||||
nir_address_format_vec2_index_32bit_offset);
|
||||
|
||||
NIR_PASS_V(nir, lower_intrinsics, key, layout);
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue