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15916 commits

Author SHA1 Message Date
Alyssa Rosenzweig
1b648326ac jay: refuse to propagate ADDRESS copies 
at least until we have address RA..

Totals:
Instrs: 2764282 -> 2764288 (+0.00%)
CodeSize: 44299872 -> 44299920 (+0.00%)

Totals from 2 (0.08% of 2647) affected shaders:
Instrs: 4215 -> 4221 (+0.14%)
CodeSize: 67456 -> 67504 (+0.07%)

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>
 2026-04-20 22:32:07 +00:00
Alyssa Rosenzweig
56ffad0c3a jay: call DCE an extra time 
Totals:
Instrs: 2767235 -> 2765908 (-0.05%); split: -0.10%, +0.05%
CodeSize: 44349488 -> 44328688 (-0.05%); split: -0.10%, +0.06%

Totals from 347 (13.11% of 2647) affected shaders:
Instrs: 718067 -> 716740 (-0.18%); split: -0.39%, +0.20%
CodeSize: 11626032 -> 11605232 (-0.18%); split: -0.39%, +0.21%

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>
 2026-04-20 22:32:06 +00:00
Alyssa Rosenzweig
d85eb51e17 jay/register_allocate: don't depend on indexing 
this can get messed up by optimizations.

Totals:
Instrs: 2768612 -> 2764317 (-0.16%); split: -0.29%, +0.13%
CodeSize: 44367648 -> 44300352 (-0.15%); split: -0.28%, +0.13%

Totals from 867 (32.75% of 2647) affected shaders:
Instrs: 1694745 -> 1690450 (-0.25%); split: -0.47%, +0.22%
CodeSize: 27387648 -> 27320352 (-0.25%); split: -0.46%, +0.21%

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>
 2026-04-20 22:32:06 +00:00
Alyssa Rosenzweig
a964f321a5 jay: don't print internal without the flag 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>
 2026-04-20 22:32:06 +00:00
Alyssa Rosenzweig
3a73c76373 jay: fix spiller coupling code 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>
 2026-04-20 22:32:05 +00:00
Alyssa Rosenzweig
cd6c5a2f90 jay: improve spiller debug 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>
 2026-04-20 22:32:05 +00:00
Alyssa Rosenzweig
d637554418 jay: fix simd32 deswizzle 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>
 2026-04-20 22:32:05 +00:00
Alyssa Rosenzweig
f728e3cb05 jay: test logic op fusing 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>
 2026-04-20 22:32:04 +00:00
Alyssa Rosenzweig
698223ccd1 jay/test-optimizer: fuse before/after cases 
new macro to DRY.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>
 2026-04-20 22:32:04 +00:00
Alyssa Rosenzweig
99796bff04 jay: fold logic ops 
Totals:
Instrs: 2798036 -> 2784419 (-0.49%); split: -0.58%, +0.10%
CodeSize: 44815024 -> 44614000 (-0.45%); split: -0.56%, +0.11%
Number of fill instructions: 2270 -> 2280 (+0.44%)

Totals from 1298 (49.04% of 2647) affected shaders:
Instrs: 2165338 -> 2151721 (-0.63%); split: -0.75%, +0.13%
CodeSize: 34865440 -> 34664416 (-0.58%); split: -0.72%, +0.15%
Number of fill instructions: 1571 -> 1581 (+0.64%)

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>
 2026-04-20 22:32:04 +00:00
Alyssa Rosenzweig
5d22e9d2a5 jay: allow predication of pure-flag instrs 
i.e. compares

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>
 2026-04-20 22:32:03 +00:00
Alyssa Rosenzweig
2ab8a614dd jay/register_allocate: tie predicated-defaults 
(if we can)

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>
 2026-04-20 22:32:03 +00:00
Alyssa Rosenzweig
d74ada78c0 jay/assign_flags: handle predicated CMP 
the optimizer will generate this soon, so make sure flag RA can deal.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>
 2026-04-20 22:32:02 +00:00
Alyssa Rosenzweig
375945ea0b jay/lower_pre_ra: skip predication 
otherwise the assert blows up

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>
 2026-04-20 22:32:02 +00:00
Alyssa Rosenzweig
176b9a0f0c jay/opt_dead_code: handle predication 
otherwise we'll get validation splat soon.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>
 2026-04-20 22:32:02 +00:00
Alyssa Rosenzweig
f63ab3eea5 jay/register_allocate: use standard builder name 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>
 2026-04-20 22:32:02 +00:00
Alyssa Rosenzweig
f98e2b24bc jay: fix the source pinning code 
I was just trying to get rid of the loop but it also generates better code.

Totals:
Instrs: 2806469 -> 2798036 (-0.30%); split: -0.33%, +0.02%
CodeSize: 44950448 -> 44815024 (-0.30%); split: -0.32%, +0.02%

Totals from 143 (5.40% of 2647) affected shaders:
Instrs: 665554 -> 657121 (-1.27%); split: -1.37%, +0.10%
CodeSize: 10611344 -> 10475920 (-1.28%); split: -1.37%, +0.10%

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>
 2026-04-20 22:32:02 +00:00
Alyssa Rosenzweig
ad731766d3 jay: fix SEL implied pipe 
Pretty obscure, but this is not valid:

< (1&W)       sync.nop _.0                                        | $2.dst
< (32&f2.0)   sel.f32 g48, g48, -g40                              | I@7
---
> (32&f2.0)   sel.f32 g48, g48, -g40                              | @7 $2.dst

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>
 2026-04-20 22:32:01 +00:00
Alyssa Rosenzweig
9b423bfe94 jay: reduce calloc to malloc when memsetting after 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>
 2026-04-20 22:32:01 +00:00
Alyssa Rosenzweig
b46d677aab jay: reduce zeroing 
this is fully initialized when constructing phi webs anyway.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>
 2026-04-20 22:32:01 +00:00
Alyssa Rosenzweig
e20f8ab2b2 jay: generalize last kill code 
Totals:
Instrs: 2815692 -> 2806469 (-0.33%); split: -0.44%, +0.11%
CodeSize: 45100624 -> 44950448 (-0.33%); split: -0.44%, +0.11%

Totals from 1292 (48.81% of 2647) affected shaders:
Instrs: 2427684 -> 2418461 (-0.38%); split: -0.51%, +0.13%
CodeSize: 38993984 -> 38843808 (-0.39%); split: -0.51%, +0.13%

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>
 2026-04-20 22:32:00 +00:00
Alyssa Rosenzweig
70bfa005a5 jay: drop dead code 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>
 2026-04-20 22:32:00 +00:00
Alyssa Rosenzweig
f39f6ce7ba jay: strengthen assert 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41064>
 2026-04-20 22:31:59 +00:00
Lionel Landwerlin
3388123f02 anv/apply_layout: move some helpers around
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No functional changes.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41047>
 2026-04-20 21:53:35 +03:00
Lionel Landwerlin
fc44be9762 anv: run a single impl loop for apply_pipeline_layout 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41047>
 2026-04-20 21:53:35 +03:00
Lionel Landwerlin
55509ac096 anv: simplify inline uniform descriptor loads 
Since e94cb92cb0 ("anv: use internal surface state on Gfx12.5+ to
access descriptor buffers") we're only using the 32bit_index_offset
address format for loads from descriptor memory.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41047>
 2026-04-20 21:53:35 +03:00
Lionel Landwerlin
730227d1a9 anv: fix relocations into internal shaders 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41047>
 2026-04-20 21:53:35 +03:00
Lionel Landwerlin
373a4df639 anv: remove unused defines 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41047>
 2026-04-20 21:53:35 +03:00
Lionel Landwerlin
9ab20cc4e4 anv: switch from INTEL_DEBUG to ANV_DEBUG for shader-print 
Only used by Anv

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41047>
 2026-04-20 21:53:35 +03:00
Lionel Landwerlin
88b4eed4f6 anv: rework debug flag 
Making it easier to use.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41047>
 2026-04-20 21:53:35 +03:00
Lionel Landwerlin
d581b7282b anv: fixup compute queue detection 
I ran into this case where genX(cmd_buffer_emit_bt_pool_base_address)
was returning immediately because it considered an RCS engine
emulating a compute queue as neither a render nor a compute queue.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41047>
 2026-04-20 21:53:35 +03:00
Lionel Landwerlin
c0c324fcb2 anv: fix debug printfs on hang 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 0932d0c7e0 ("anv/xe: rework set_lost handling in xe_exec_ioctl()")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41047>
 2026-04-20 21:53:35 +03:00
Lionel Landwerlin
3256fab5a3 anv: fix invalid value for push block index 
Probably worked because we could always reach to things through the
binding table and the index was the same.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41047>
 2026-04-20 21:53:35 +03:00
Lionel Landwerlin
773fef12cd anv: fix compute push constant allocations on pre Gfx12.5 platforms 
MEDIA_CURBE_LOAD::CURBETotalDataLength needs to be 64B aligned.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41047>
 2026-04-20 21:53:35 +03:00
Lionel Landwerlin
f6306198d0 anv: avoid C23 
For some reason the android builders started noticing...

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41047>
 2026-04-20 21:53:35 +03:00
Lionel Landwerlin
13f5531692 intel/dev: fixup intel_needs_workaround() macro 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41047>
 2026-04-20 21:53:35 +03:00
Tapani Pälli
8736d1a9a6 intel/compiler: implement macl part of Wa_18035690555
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Fixes: 3ab9145393 ("intel/compiler: implement dummy mov for Wa_18035690555")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40941>
 2026-04-19 11:39:10 +00:00
Matt Turner
d36a578bc0 intel/elk: Remove dead TXL_LZ/TXF_LZ opcodes
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These opcodes were only emitted for Gen9+ hardware, but elk only targets
Gen8 and below.

Fixes: 05d78994a7 ("intel/elk: Remove Gfx9+ sampler messages and modes")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41009>
 2026-04-17 15:13:00 +00:00
Matt Turner
6856ebe00d intel/elk: Remove some dead code 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41009>
 2026-04-17 15:13:00 +00:00
Sagar Ghuge
19d64d6f7d anv/rt: Copy 16bytes at once instead of copying 8bytes
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For simple copy, we can copy data with uvec4(16bytes) at once.
When we have serialize/deserialize copy mode, we want to copy out the
instance leave address which are 8byte wide, so we need to jump with
8byte stride instead of 16bytes.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40966>
 2026-04-16 02:52:03 +00:00
Mauro Rossi
cc44922048 intel/jay: fix static_assert expression
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Fixes the following building error:

FAILED: src/intel/compiler/jay/libintel_compiler_jay.a.p/jay_assign_flags.c.o
...
In file included from ../src/intel/compiler/jay/jay_assign_flags.c:6:
../src/intel/compiler/jay/jay_builder.h:184:24: error: static_assert expression is not an integral constant expression
         static_assert(sizeof(uintptr_t) <= sizeof(uint64_t) &&
                       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1 error generated.

Fixes: e42e3193 ("intel: add Jay")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40960>
 2026-04-14 23:14:07 +00:00
Alyssa Rosenzweig
1b029f3279 jay: allow cmod on cvt 
it's just a MOV

saves an instruction on dEQP-GLES31.functional.compute.basic.image_atomic_op_local_size_8

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40960>
 2026-04-14 23:14:07 +00:00
Alyssa Rosenzweig
9df62df55e jay: fix bfn cmod 
affects dEQP-GLES31.functional.compute.basic.image_atomic_op_local_size_8

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40960>
 2026-04-14 23:14:07 +00:00
Alyssa Rosenzweig
b9f8467855 jay: fix a bunch of opcode properties 
really need a full audit..

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40960>
 2026-04-14 23:14:07 +00:00
Alyssa Rosenzweig
8afcbbe77d jay: load_simd_width_intel 
dEQP-GLES31.functional.shaders.arrays_of_arrays.es31.array_access.dynamic_expression_access_fragment

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40960>
 2026-04-14 23:14:07 +00:00
Alyssa Rosenzweig
4eb838eb48 jay: split up jay_from_nir.c 
Big monolithic file, split it up into the relevant pieces.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40960>
 2026-04-14 23:14:07 +00:00
Alyssa Rosenzweig
6925d9ee23 jay: move deswizzle hack outside of swsb 
this will eventually enable better swsb for the simd32 payload code.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40960>
 2026-04-14 23:14:07 +00:00
Alyssa Rosenzweig
48a24f3c27 jay: fix instr counts 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40960>
 2026-04-14 23:14:07 +00:00
Kenneth Graunke
3a1227f36b jay: Clear default group for quad swizzles 
Quad swizzles should always execute with NoMask and group 0.

We skipped initializing the group, and so inherited whatever the state
from the previous instruction was.  This led to incorrect behavior if
the previous instruction was SIMD split:

   (16)        mov.u32 g84<2>, g2        |
   (16|M16)    mov.u32 g86<2>, g3        |
   (32|M16&W)  mov.u32 g2, g126.2<4,4,0> | I@1

Oops.  The final quad swizzle shouldn't have had M16 set.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40960>
 2026-04-14 23:14:07 +00:00
Kenneth Graunke
8bfb139033 jay: Make lower_immediates bail if there are no sources 
For example, JAY_OPCODE_PRELOAD has no sources.  Reading src[other]
would read uninitialized data.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40960>
 2026-04-14 23:14:07 +00:00