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intel/compiler: implement macl part of Wa_18035690555
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Fixes: 3ab9145393 ("intel/compiler: implement dummy mov for Wa_18035690555")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40941>
This commit is contained in:
Tapani Pälli 2026-04-09 11:12:16 +03:00 • committed by Marge Bot
parent 98a97cb413
commit 8736d1a9a6
1 changed files with 36 additions and 12 deletions
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48
src/intel/compiler/brw/brw_workaround.cpp
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@ -38,13 +38,17 @@ brw_workaround_emit_dummy_mov_instruction(brw_shader &s)
/* Wa_18035690555
*
* If we have mul <-> mac or macl <-> mach and src1 is the same in current
* and previous inst, we need to insert a dummy mov in between. We can skip
* issue 2 mentioned in wa as macl is not used by our compiler.
* Issue 1: If we have mul <-> mac or macl <-> mach and src1 is
* the same in current and previous inst, we need to insert a
* dummy mov in between.
*
* Other conditions listed in the issue for mul <-> mac case:
* "prev instruction src1 has regioning/scalar" (not flat)
* "current instruction src1 is flat and shares the same src1 as prev"
*
* Issue 2: prev inst is non-mul or non-macl and src1 is
* the same in current and previous inst, we need to insert a
* dummy mov in between.
*/
bool
brw_workaround_emit_dummy_mov_mulmac(brw_shader &s)
@ -55,7 +59,7 @@ brw_workaround_emit_dummy_mov_mulmac(brw_shader &s)
#define IS_MUL_CLASS(x) \
(x->opcode == BRW_OPCODE_MUL || x->opcode == BRW_OPCODE_MAC)
#define IS_MACL_CLASS(x) \
(x->opcode == BRW_OPCODE_MACH)
(x->opcode == BRW_OPCODE_MACH || x->opcode == BRW_OPCODE_MACL)
#define IS_FLAT(x, i) (x->dst.subnr == x->src[i].subnr && \
x->src[i].is_contiguous())
@ -63,19 +67,39 @@ brw_workaround_emit_dummy_mov_mulmac(brw_shader &s)
brw_inst *prev_inst = NULL;
bool progress = false;
foreach_block_and_inst_safe (block, brw_inst, inst, s.cfg) {
if (prev_inst &&
inferred_exec_pipe(s.devinfo, inst) ==
inferred_exec_pipe(s.devinfo, prev_inst) &&
((IS_MUL_CLASS(inst) && IS_MUL_CLASS(prev_inst)) ||
if (!prev_inst ||
(inferred_exec_pipe(s.devinfo, inst) !=
inferred_exec_pipe(s.devinfo, prev_inst))) {
prev_inst = inst;
continue;
}
bool emit_mov = false;
/* Issue 1 */
if (((IS_MUL_CLASS(inst) && IS_MUL_CLASS(prev_inst)) ||
(IS_MACL_CLASS(inst) && IS_MACL_CLASS(prev_inst))) &&
(IS_FLAT(inst, 1) && !IS_FLAT(prev_inst, 1)) &&
(phys_nr(s.devinfo, inst->src[1]) ==
phys_nr(s.devinfo, prev_inst->src[1])) &&
(IS_FLAT(inst, 1) && !IS_FLAT(prev_inst, 1))) {
/* Insert dummy mov between prev and current inst. */
const brw_builder ubld = brw_builder(prev_inst).exec_all().group(8, 0);
phys_nr(s.devinfo, prev_inst->src[1]))) {
emit_mov = true;
}
/* Issue 2 */
else if ((!IS_MUL_CLASS(prev_inst) && !IS_MACL_CLASS(prev_inst)) &&
(IS_MACL_CLASS(inst) && IS_FLAT(inst, 1)) &&
(prev_inst->sources && phys_nr(s.devinfo, inst->src[1]) ==
phys_nr(s.devinfo, prev_inst->src[1]))) {
emit_mov = true;
}
/* Insert dummy mov between prev and current inst. */
if (emit_mov) {
const brw_builder ubld = brw_builder(inst).exec_all().group(8, 0);
ubld.MOV(ubld.null_reg_ud(), brw_imm_ud(0u));
progress = true;
}
prev_inst = inst;
}