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anv/apply_layout: move some helpers around
No functional changes. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41047>
This commit is contained in:
Lionel Landwerlin
parent
fc44be9762
commit
3388123f02
1 changed files with 103 additions and 103 deletions
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@ -322,6 +322,109 @@ get_used_bindings(UNUSED nir_builder *_b, nir_instr *instr, void *_state)
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return false;
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}
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static nir_def *
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build_load_desc_set_dynamic_index(nir_builder *b, unsigned set_idx)
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{
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return nir_iand_imm(
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b,
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anv_load_driver_uniform(b, 1, desc_surface_offsets[set_idx]),
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ANV_DESCRIPTOR_SET_DYNAMIC_INDEX_MASK);
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}
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/** Build a Vulkan resource index
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*
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* A "resource index" is the term used by our SPIR-V parser and the relevant
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* NIR intrinsics for a reference into a descriptor set. It acts much like a
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* deref in NIR except that it accesses opaque descriptors instead of memory.
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*
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* Coming out of SPIR-V, both the resource indices (in the form of
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* vulkan_resource_[re]index intrinsics) and the memory derefs (in the form
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* of nir_deref_instr) use the same vector component/bit size. The meaning
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* of those values for memory derefs (nir_deref_instr) is given by the
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* nir_address_format associated with the descriptor type. For resource
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* indices, it's an entirely internal to ANV encoding which describes, in some
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* sense, the address of the descriptor. Thanks to the NIR/SPIR-V rules, it
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* must be packed into the same size SSA values as a memory address. For this
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* reason, the actual encoding may depend both on the address format for
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* memory derefs and the descriptor address format.
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*
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* The load_vulkan_descriptor intrinsic exists to provide a transition point
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* between these two forms of derefs: descriptor and memory.
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*/
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static nir_def *
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build_res_index(nir_builder *b,
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uint32_t set, uint32_t binding,
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nir_def *array_index,
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const struct apply_pipeline_layout_state *state)
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{
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const struct anv_descriptor_set_binding_layout *bind_layout =
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&state->set_layouts[set]->binding[binding];
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assert(bind_layout->dynamic_offset_index < MAX_DYNAMIC_BUFFERS);
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nir_def *dynamic_offset_index;
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if (bind_layout->dynamic_offset_index >= 0) {
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if (state->dynamic_offset_start == NULL) {
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nir_def *dynamic_offset_start =
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build_load_desc_set_dynamic_index(b, set);
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dynamic_offset_index =
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nir_iadd_imm(b, dynamic_offset_start,
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bind_layout->dynamic_offset_index);
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} else {
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dynamic_offset_index =
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nir_imm_int(b,
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state->dynamic_offset_start[set] +
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bind_layout->dynamic_offset_index);
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}
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} else {
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dynamic_offset_index = nir_imm_int(b, 0xff); /* No dynamic offset */
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}
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/* We don't care about the stride field for inline uniforms (see
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* build_desc_addr_for_res_index), but for anything else we should be
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* aligned to 8 bytes because we store a multiple of 8 in the packed info
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* to be able to encode a stride up to 2040 (8 * 255).
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*/
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assert(bind_layout->type == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK ||
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bind_layout->descriptor_surface_stride % 8 == 0);
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const uint32_t desc_stride =
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bind_layout->type == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK ? 0 :
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bind_layout->descriptor_surface_stride / 8;
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nir_def *packed =
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nir_ior_imm(b,
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dynamic_offset_index,
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(desc_stride << 8));
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return nir_vec4(b,
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nir_imm_int(b, set),
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packed,
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nir_imm_int(b, bind_layout->descriptor_surface_offset),
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array_index);
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}
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struct res_index_defs {
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nir_def *bti_idx;
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nir_def *set;
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nir_def *dyn_offset_base;
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nir_def *desc_offset_base;
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nir_def *array_index;
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nir_def *desc_stride;
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};
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static struct res_index_defs
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unpack_res_index(nir_builder *b, nir_def *index)
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{
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nir_def *packed = nir_channel(b, index, 1);
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return (struct res_index_defs) {
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.set = nir_channel(b, index, 0),
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.desc_stride = nir_imul_imm(b, nir_extract_u8_imm(b, packed, 1), 8),
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.dyn_offset_base = nir_extract_u8_imm(b, packed, 0),
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.desc_offset_base = nir_channel(b, index, 2),
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.array_index = nir_channel(b, index, 3),
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};
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}
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static nir_intrinsic_instr *
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find_descriptor_for_index_src(nir_src src,
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struct apply_pipeline_layout_state *state)
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@ -590,15 +693,6 @@ build_load_storage_3d_image_depth(nir_builder *b,
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}
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}
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static nir_def *
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build_load_desc_set_dynamic_index(nir_builder *b, unsigned set_idx)
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{
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return nir_iand_imm(
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b,
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anv_load_driver_uniform(b, 1, desc_surface_offsets[set_idx]),
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ANV_DESCRIPTOR_SET_DYNAMIC_INDEX_MASK);
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}
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/** Build a 64bit_global_32bit_offset address for a descriptor set */
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static nir_def *
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build_desc_address64(nir_builder *b, nir_def *set_idx, unsigned set_idx_imm,
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@ -696,100 +790,6 @@ build_desc_address32(nir_builder *b,
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offset));
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}
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/** Build a Vulkan resource index
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*
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* A "resource index" is the term used by our SPIR-V parser and the relevant
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* NIR intrinsics for a reference into a descriptor set. It acts much like a
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* deref in NIR except that it accesses opaque descriptors instead of memory.
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*
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* Coming out of SPIR-V, both the resource indices (in the form of
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* vulkan_resource_[re]index intrinsics) and the memory derefs (in the form
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* of nir_deref_instr) use the same vector component/bit size. The meaning
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* of those values for memory derefs (nir_deref_instr) is given by the
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* nir_address_format associated with the descriptor type. For resource
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* indices, it's an entirely internal to ANV encoding which describes, in some
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* sense, the address of the descriptor. Thanks to the NIR/SPIR-V rules, it
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* must be packed into the same size SSA values as a memory address. For this
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* reason, the actual encoding may depend both on the address format for
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* memory derefs and the descriptor address format.
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*
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* The load_vulkan_descriptor intrinsic exists to provide a transition point
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* between these two forms of derefs: descriptor and memory.
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*/
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static nir_def *
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build_res_index(nir_builder *b,
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uint32_t set, uint32_t binding,
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nir_def *array_index,
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struct apply_pipeline_layout_state *state)
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{
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const struct anv_descriptor_set_binding_layout *bind_layout =
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&state->set_layouts[set]->binding[binding];
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assert(bind_layout->dynamic_offset_index < MAX_DYNAMIC_BUFFERS);
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nir_def *dynamic_offset_index;
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if (bind_layout->dynamic_offset_index >= 0) {
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if (state->dynamic_offset_start == NULL) {
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nir_def *dynamic_offset_start =
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build_load_desc_set_dynamic_index(b, set);
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dynamic_offset_index =
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nir_iadd_imm(b, dynamic_offset_start,
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bind_layout->dynamic_offset_index);
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} else {
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dynamic_offset_index =
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nir_imm_int(b,
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state->dynamic_offset_start[set] +
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bind_layout->dynamic_offset_index);
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}
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} else {
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dynamic_offset_index = nir_imm_int(b, 0xff); /* No dynamic offset */
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}
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/* We don't care about the stride field for inline uniforms (see
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* build_desc_addr_for_res_index), but for anything else we should be
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* aligned to 8 bytes because we store a multiple of 8 in the packed info
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* to be able to encode a stride up to 2040 (8 * 255).
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*/
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assert(bind_layout->type == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK ||
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bind_layout->descriptor_surface_stride % 8 == 0);
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const uint32_t desc_stride =
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bind_layout->type == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK ? 0 :
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bind_layout->descriptor_surface_stride / 8;
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nir_def *packed =
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nir_ior_imm(b,
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dynamic_offset_index,
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(desc_stride << 8));
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return nir_vec4(b,
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nir_imm_int(b, set),
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packed,
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nir_imm_int(b, bind_layout->descriptor_surface_offset),
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array_index);
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}
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struct res_index_defs {
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nir_def *bti_idx;
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nir_def *set;
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nir_def *dyn_offset_base;
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nir_def *desc_offset_base;
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nir_def *array_index;
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nir_def *desc_stride;
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};
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static struct res_index_defs
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unpack_res_index(nir_builder *b, nir_def *index)
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{
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nir_def *packed = nir_channel(b, index, 1);
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return (struct res_index_defs) {
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.set = nir_channel(b, index, 0),
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.desc_stride = nir_imul_imm(b, nir_extract_u8_imm(b, packed, 1), 8),
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.dyn_offset_base = nir_extract_u8_imm(b, packed, 0),
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.desc_offset_base = nir_channel(b, index, 2),
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.array_index = nir_channel(b, index, 3),
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};
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}
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/** Whether a surface is accessed through the bindless surface state heap */
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static bool
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is_binding_bindless(unsigned set, unsigned binding, bool sampler,
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