mirror of
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anv: simplify inline uniform descriptor loads
Since e94cb92cb0 ("anv: use internal surface state on Gfx12.5+ to
access descriptor buffers") we're only using the 32bit_index_offset
address format for loads from descriptor memory.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41047>
This commit is contained in:
Lionel Landwerlin
parent
730227d1a9
commit
55509ac096
1 changed files with 37 additions and 132 deletions
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@ -56,7 +56,6 @@ struct apply_pipeline_layout_state {
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const uint32_t *dynamic_offset_start;
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nir_address_format desc_addr_format;
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nir_address_format ssbo_addr_format;
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nir_address_format ubo_addr_format;
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@ -401,8 +400,6 @@ build_load_descriptor_mem(nir_builder *b,
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const struct apply_pipeline_layout_state *state)
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{
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assert(state->desc_addr_format == nir_address_format_32bit_index_offset);
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nir_def *surface_index = nir_channel(b, desc_addr, 0);
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nir_def *offset32 = nir_iadd_imm(b, nir_channel(b, desc_addr, 1), desc_offset);
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@ -839,51 +836,15 @@ build_res_reindex(nir_builder *b, nir_def *orig, nir_def *delta)
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*/
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static nir_def *
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build_desc_addr_for_res_index(nir_builder *b,
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const VkDescriptorType desc_type,
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nir_def *index, nir_address_format addr_format,
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struct apply_pipeline_layout_state *state)
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{
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struct res_index_defs res = unpack_res_index(b, index);
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nir_def *desc_offset = res.desc_offset_base;
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if (desc_type != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK) {
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/* Compute the actual descriptor offset. For inline uniform blocks,
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* the array index is ignored as they are only allowed to be a single
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* descriptor (not an array) and there is no concept of a "stride".
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*
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*/
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desc_offset =
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nir_iadd(b, desc_offset, nir_imul(b, res.array_index, res.desc_stride));
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}
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switch (addr_format) {
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case nir_address_format_64bit_global_32bit_offset:
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case nir_address_format_64bit_bounded_global: {
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switch (state->desc_addr_format) {
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case nir_address_format_64bit_global_32bit_offset: {
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nir_def *base_addr = build_desc_address64(b, res.set, UINT32_MAX, state);
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return nir_vec4(b, nir_unpack_64_2x32_split_x(b, base_addr),
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nir_unpack_64_2x32_split_y(b, base_addr),
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nir_imm_int(b, UINT32_MAX),
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desc_offset);
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}
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case nir_address_format_32bit_index_offset:
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return build_desc_address32(b, res.set, UINT32_MAX, desc_offset, state);
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default:
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UNREACHABLE("Unhandled address format");
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}
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}
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case nir_address_format_32bit_index_offset:
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assert(desc_type == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK);
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assert(state->desc_addr_format == nir_address_format_32bit_index_offset);
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return build_desc_address32(b, res.set, UINT32_MAX, desc_offset, state);
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default:
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UNREACHABLE("Unhandled address format");
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}
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nir_def *desc_offset = nir_iadd(b,
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res.desc_offset_base,
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nir_imul(b, res.array_index, res.desc_stride));
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return build_desc_address32(b, res.set, UINT32_MAX, desc_offset, state);
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}
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static nir_def *
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@ -895,44 +856,30 @@ build_desc_addr_for_binding(nir_builder *b,
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const struct anv_descriptor_set_binding_layout *bind_layout =
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&state->set_layouts[set]->binding[binding];
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switch (state->desc_addr_format) {
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case nir_address_format_64bit_global_32bit_offset:
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case nir_address_format_64bit_bounded_global: {
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nir_def *base_addr = build_desc_address64(b, NULL, set, state);
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nir_def *desc_offset =
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nir_iadd_imm(b,
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nir_imul_imm(b,
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array_index,
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bind_layout->descriptor_surface_stride),
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bind_layout->descriptor_surface_offset);
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if (plane != 0) {
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desc_offset = nir_iadd_imm(
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b, desc_offset, plane * bind_layout->descriptor_data_surface_size);
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}
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return nir_vec4(b, nir_unpack_64_2x32_split_x(b, base_addr),
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nir_unpack_64_2x32_split_y(b, base_addr),
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nir_imm_int(b, UINT32_MAX),
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desc_offset);
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nir_def *desc_offset =
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nir_iadd_imm(b,
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nir_imul_imm(b,
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array_index,
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bind_layout->descriptor_surface_stride),
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bind_layout->descriptor_surface_offset);
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if (plane != 0) {
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desc_offset = nir_iadd_imm(
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b, desc_offset, plane * bind_layout->descriptor_data_surface_size);
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}
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return build_desc_address32(b, NULL, set, desc_offset, state);
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}
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case nir_address_format_32bit_index_offset: {
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nir_def *desc_offset =
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nir_iadd_imm(b,
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nir_imul_imm(b,
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array_index,
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bind_layout->descriptor_surface_stride),
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bind_layout->descriptor_surface_offset);
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if (plane != 0) {
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desc_offset = nir_iadd_imm(
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b, desc_offset, plane * bind_layout->descriptor_data_surface_size);
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}
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return build_desc_address32(b, NULL, set, desc_offset, state);
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}
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default:
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UNREACHABLE("Unhandled address format");
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}
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static nir_def *
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build_inline_desc_addr32(nir_builder *b,
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unsigned set,
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const struct anv_descriptor_set_binding_layout *bind_layout,
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const struct apply_pipeline_layout_state *state)
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{
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return nir_vec2(
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b,
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nir_load_array_var_imm(b, state->set_idx_to_bti, set),
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nir_iadd_imm(b, nir_load_array_var_imm(b, state->set_idx_to_offset, set),
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bind_layout->descriptor_surface_offset));
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}
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static unsigned
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@ -1151,25 +1098,14 @@ build_buffer_dynamic_offset_for_res_index(nir_builder *b,
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*/
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static nir_def *
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build_indirect_buffer_addr_for_res_index(nir_builder *b,
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const VkDescriptorType desc_type,
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nir_def *res_index,
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nir_address_format addr_format,
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struct apply_pipeline_layout_state *state)
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{
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struct res_index_defs res = unpack_res_index(b, res_index);
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if (desc_type == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK) {
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assert(addr_format == state->desc_addr_format);
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return build_desc_addr_for_res_index(b, desc_type, res_index,
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addr_format, state);
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} else if (addr_format == nir_address_format_32bit_index_offset) {
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return build_desc_address32(b, res.bti_idx, UINT32_MAX,
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nir_imm_int(b, 0), state);
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}
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nir_def *desc_addr =
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build_desc_addr_for_res_index(b, desc_type, res_index,
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addr_format, state);
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build_desc_addr_for_res_index(b, res_index, addr_format, state);
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nir_def *desc = build_load_descriptor_mem(b, desc_addr, 0, 4, 32, state);
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@ -1212,16 +1148,11 @@ build_indirect_buffer_addr_for_res_index(nir_builder *b,
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static nir_def *
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build_direct_buffer_addr_for_res_index(nir_builder *b,
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const VkDescriptorType desc_type,
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nir_def *res_index,
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nir_address_format addr_format,
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struct apply_pipeline_layout_state *state)
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{
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if (desc_type == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK) {
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assert(addr_format == state->desc_addr_format);
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return build_desc_addr_for_res_index(b, desc_type, res_index,
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addr_format, state);
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} else if (addr_format == nir_address_format_32bit_index_offset) {
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if (addr_format == nir_address_format_32bit_index_offset) {
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struct res_index_defs res = unpack_res_index(b, res_index);
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return build_desc_address32(b, res.set, UINT32_MAX,
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@ -1231,8 +1162,7 @@ build_direct_buffer_addr_for_res_index(nir_builder *b,
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}
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nir_def *desc_addr =
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build_desc_addr_for_res_index(b, desc_type, res_index,
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addr_format, state);
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build_desc_addr_for_res_index(b, res_index, addr_format, state);
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nir_def *addr =
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build_load_render_surface_state_address(b, desc_addr, state);
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@ -1272,37 +1202,36 @@ build_direct_buffer_addr_for_res_index(nir_builder *b,
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static nir_def *
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build_buffer_addr_for_res_index(nir_builder *b,
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const VkDescriptorType desc_type,
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nir_def *res_index,
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nir_address_format addr_format,
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struct apply_pipeline_layout_state *state)
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{
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if (state->bind_map->layout_type == ANV_PIPELINE_DESCRIPTOR_SET_LAYOUT_TYPE_INDIRECT)
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return build_indirect_buffer_addr_for_res_index(b, desc_type, res_index, addr_format, state);
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return build_indirect_buffer_addr_for_res_index(b, res_index, addr_format, state);
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else
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return build_direct_buffer_addr_for_res_index(b, desc_type, res_index, addr_format, state);
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return build_direct_buffer_addr_for_res_index(b, res_index, addr_format, state);
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}
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static nir_def *
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build_buffer_addr_for_binding(nir_builder *b,
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const VkDescriptorType desc_type,
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unsigned set,
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unsigned binding,
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nir_def *res_index,
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nir_address_format addr_format,
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struct apply_pipeline_layout_state *state)
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{
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if (addr_format != nir_address_format_32bit_index_offset)
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return build_buffer_addr_for_res_index(b, desc_type, res_index, addr_format, state);
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const struct anv_descriptor_set_binding_layout *bind_layout =
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&state->set_layouts[set]->binding[binding];
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if (bind_layout->type == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK) {
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return build_desc_address32(b, NULL, set,
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nir_imm_int(b, bind_layout->descriptor_surface_offset),
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state);
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}
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if (addr_format != nir_address_format_32bit_index_offset)
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return build_buffer_addr_for_res_index(b, res_index, addr_format, state);
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struct res_index_defs res = unpack_res_index(b, res_index);
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return nir_vec2(b,
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@ -1388,11 +1317,7 @@ build_buffer_addr_for_idx_intrin(nir_builder *b,
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nir_def *res_index =
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build_res_index_for_chain(b, idx_intrin, &set, &binding, state);
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const struct anv_descriptor_set_binding_layout *bind_layout =
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&state->set_layouts[set]->binding[binding];
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return build_buffer_addr_for_binding(b, bind_layout->type,
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set, binding, res_index,
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return build_buffer_addr_for_binding(b, set, binding, res_index,
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addr_format, state);
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}
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@ -1633,21 +1558,6 @@ lower_res_reindex_intrinsic(nir_builder *b, nir_intrinsic_instr *intrin,
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return true;
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}
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static VkDescriptorType
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nir_to_vk_descriptor_type(nir_descriptor_type type)
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{
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switch (type) {
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case nir_descriptor_type_uniform_buffer:
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return VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER;
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case nir_descriptor_type_storage_buffer:
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return VK_DESCRIPTOR_TYPE_STORAGE_BUFFER;
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case nir_descriptor_type_acceleration_structure:
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return VK_DESCRIPTOR_TYPE_ACCELERATION_STRUCTURE_KHR;
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default:
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UNREACHABLE("Invalid nir_descriptor_type");
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}
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}
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static bool
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lower_load_vulkan_descriptor(nir_builder *b, nir_intrinsic_instr *intrin,
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struct apply_pipeline_layout_state *state)
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@ -1655,13 +1565,10 @@ lower_load_vulkan_descriptor(nir_builder *b, nir_intrinsic_instr *intrin,
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b->cursor = nir_before_instr(&intrin->instr);
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const nir_descriptor_type desc_type = nir_intrinsic_desc_type(intrin);
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const VkDescriptorType vk_desc_type = nir_to_vk_descriptor_type(desc_type);
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nir_address_format addr_format = addr_format_for_desc_type(desc_type, state);
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nir_def *desc =
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build_buffer_addr_for_res_index(b,
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vk_desc_type, intrin->src[0].ssa,
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addr_format, state);
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build_buffer_addr_for_res_index(b, intrin->src[0].ssa, addr_format, state);
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assert(intrin->def.bit_size == desc->bit_size);
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assert(intrin->def.num_components == desc->num_components);
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@ -1686,7 +1593,6 @@ lower_get_ssbo_size(nir_builder *b, nir_intrinsic_instr *intrin,
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nir_build_addr_iadd_imm(
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b,
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build_desc_addr_for_res_index(b,
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VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
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intrin->src[0].ssa,
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addr_format, state),
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addr_format,
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@ -2569,7 +2475,6 @@ anv_nir_apply_pipeline_layout(nir_shader *shader,
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.set_layouts = set_layouts,
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.set_count = set_count,
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.dynamic_offset_start = dynamic_offset_start,
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.desc_addr_format = nir_address_format_32bit_index_offset,
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.ssbo_addr_format = anv_nir_ssbo_addr_format(pdevice, robust_flags),
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.ubo_addr_format = anv_nir_ubo_addr_format(pdevice, robust_flags),
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};
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