Commit graph

57904 commits

Author SHA1 Message Date
Ilia Mirkin
bd304ffc85 nv50: Fix GPU_READING/WRITING bit removal
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
CC: "9.1, 9.2, 10.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit c45cf6199f)
2013-12-12 15:40:48 -08:00
Chad Versace
16c5f24141 i965: Add extra-alignment for non-msrt fast color clear for all hw (v2)
The BSpec states that the aligment for the non-msrt clear rectangle must
be doubled; the BSpec does not restricit the workaround to specific
hardware.

Commit 9a1a67b applied the workaround to Haswell GT3.  Commit 8b659ce
expanded the workaround to all Haswell variants. This commit expands it
to all hardware.

No Piglit regressions on Ivybridge 0x0166. No fixes either.

I know no Ivybridge nor Baytrail bug related to this workaround.
However, the BSpec says the extra alignment is required, so let's do it.

v2: Apply to all hardware, not just gen7.

CC: "9.2, 10.0" <mesa-stable@lists.freedesktop.org>
CC: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
(cherry picked from commit 998018d7be)
2013-12-12 15:40:24 -08:00
Chad Versace
b60eb2e174 i965/hsw: Apply non-msrt fast color clear w/a to all HSW GTs
Pre-patch, the workaround was applied to only HSW GT3. However, the
workaround also fixes render corruption on the HSW GT1 Chromebook,
codenamed Falco.

Also, update the BSpec quote that discusses the workaround to reflect
the latest BSpec.

The BSpec states that the workaround is required for Ivybridge and
Baytrail as well as Haswell. But, we apply the workaround to only
Haswell because (a) we suspect that is the only hardware where it is
actually required and (b) we haven't yet validated the workaround for
the other hardware.

CC: "9.2, 10.0" <mesa-stable@lists.freedesktop.org>
CC: Anuj Phogat <anuj.phogat@gmail.com>
OTC-Tracker: CHRMOS-812
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
(cherry picked from commit 8b659cef3a)
2013-12-12 15:39:45 -08:00
Carl Worth
ebe8e9b01f docs: Add md5sums for the 9.2.4 release
Just after tagging the 9.2.4 release and making the tar files.
2013-11-27 23:52:54 -08:00
Carl Worth
3e385d1bc3 docs: Add release notes for the 9.2.4 release. 2013-11-27 23:41:14 -08:00
Carl Worth
bd62562282 Bump version to 9.2.4
In preparation for the 9.2.4 release.
2013-11-27 23:37:50 -08:00
Paul Berry
6a022c8b03 glsl: Fix lowering of direct assignment in lower_clip_distance.
In commit 065da16 (glsl: Convert lower_clip_distance_visitor to be an
ir_rvalue_visitor), we failed to notice that since
lower_clip_distance_visitor overrides visit_leave(ir_assignment *),
ir_rvalue_visitor::visit_leave(ir_assignment *) wasn't getting called.
As a result, clip distance dereferences appearing directly on the
right hand side of an assignment (not in a subexpression) weren't
getting properly lowered.  This caused an ir_dereference_variable node
to be left in the IR that referred to the old gl_ClipDistance
variable.  However, since the lowering pass replaces gl_ClipDistance
with gl_ClipDistanceMESA, this turned into a dangling pointer when the
IR got reparented.

Prior to the introduction of geometry shaders, this bug was unlikely
to arise, because (a) reading from gl_ClipDistance[i] in the fragment
shader was rare, and (b) when it happened, it was likely that it would
either appear in a subexpression, or be hoisted into a subexpression
by tree grafting.

However, in a geometry shader, we're likely to see a statement like
this, which would trigger the bug:

    gl_ClipDistance[i] = gl_in[j].gl_ClipDistance[i];

This patch causes
lower_clip_distance_visitor::visit_leave(ir_assignment *) to call the
base class visitor, so that the right hand side of the assignment is
properly lowered.

Fixes piglit test:
- spec/glsl-1.50/execution/geometry/clip-distance-itemized-copy

Cc: Ian Romanick <idr@freedesktop.org>
Cc: "9.2" <mesa-stable@lists.freedesktop.org>
Cc: "10.0" <mesa-stable@lists.freedesktop.org>

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
(cherry picked from commit 9dfcb05fa6)
2013-11-26 16:39:13 -08:00
Tapani Pälli
dfaf5de460 mesa: enable GL_TEXTURE_LOD_BIAS set/get
Earlier comments suggest this was removed from GL core spec but it is
still there. Enabling makes 'texture_lod_bias_getter' Khronos
conformance tests pass, also removes some errors from Metro Last Light
game which is using this API.

v2: leave NOTE comment (Ian)

Cc: "9.0 9.1 9.2 10.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
(cherry picked from commit 7e61b44dcd)
2013-11-26 16:30:45 -08:00
Brian Paul
b9990d758b st/mesa: fix GL_FEEDBACK mode inverted Y coordinate bug
We need to check the drawbuffer's orientation before inverting Y
coordinates.  Fixes piglit feedback tests when running with the
-fbo option.

Cc: "9.2" "10.0" <mesa-stable@lists.freedesktop.org>

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit 15d8e05e1e)
2013-11-26 16:30:07 -08:00
Paul Berry
ee5e7148e5 i965: Fix vertical alignment for multisampled buffers.
From the Sandy Bridge PRM, Vol 1 Part 1 7.18.3.4 (Alignment Unit
Size):

    j [vertical alignment] = 4 for any render target surface is
    multisampled (4x)

From the Ivy Bridge PRM, Vol 4 Part 1 2.12.2.1 (SURFACE_STATE for most
messages), under the "Surface Vertical Alignment" heading:

    This field is intended to be set to VALIGN_4 if the surface was
    rendered as a depth buffer, for a multisampled (4x) render target,
    or for a multisampled (8x) render target, since these surfaces
    support only alignment of 4.

Back in 2012 when we added multisampling support to the i965 driver,
we forgot to update the logic for computing the vertical alignment, so
we were often using a vertical alignment of 2 for multisampled
buffers, leading to subtle rendering errors.

Note that the specs also require a vertical alignment of 4 for all
Y-tiled render target surfaces; I plan to address that in a separate
patch.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=53077
Cc: mesa-stable@lists.freedesktop.org

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit b4c3b833ec)
2013-11-26 16:27:32 -08:00
Carl Worth
44831bff0f Merge branch '9.2-freedreno' of git://github.com/freedreno/mesa into 9.2
This allows the freedreno driver to build with current mesa.
2013-11-26 16:25:06 -08:00
Rob Clark
4fd03f26aa freedreno: updates for msm drm/kms driver
There where some small API tweaks in libdrm_freedreno to enable support
for msm drm/kms driver.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2013-11-13 10:16:02 -05:00
Rob Clark
4f0be333e7 freedreno/a3xx/compiler: handle sync flags better
We need to set the flag on all the .xyzw components that are written by
the instruction, not just on .x.  Otherwise a later use of rN.y (for
example) will not trigger the appropriate sync bit to be set.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2013-11-13 10:16:02 -05:00
Rob Clark
f1998c8aa7 freedreno/a3xx/compiler: better const handling
Seems like most/all instructions have some restrictions about const src
registers.  In seems like the 2 src (cat2) instructions can take at most
one const, and the 3 src (cat3) instructions can take at most one const
in the first 2 arguments.  And so on.  Handle this properly now.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2013-11-13 10:16:01 -05:00
Rob Clark
0b2c5119cb freedreno/a3xx: don't leak so much
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2013-11-13 10:16:01 -05:00
Rob Clark
c20aa295ec freedreno/a3xx/compiler: fix SGT/SLT/etc
The cmps.f.* instruction doesn't actually seem to give a float 1.0 or
0.0 output.  It either needs a cov.u16f16 or add.s + sel.f16.  This
makes SGT/SLT/etc more similar to CMP, so handle them in trans_cmp().

This fixes a bunch of piglit tests.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2013-11-13 10:16:01 -05:00
Rob Clark
ca5514b851 freedreno/a3xx/compiler: bit of re-arrange/cleanup
It seems there are a number of cases where instructions have limitations
about taking reading src's from const register file, so make
get_unconst() a bit easier to use.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2013-11-13 10:16:01 -05:00
Rob Clark
c726a6a907 freedreno/a3xx/compiler: make compiler errors more useful
We probably should get rid of assert() entirely, but at this stage it is
more useful for things to crash where we can catch it in a debugger.
With compile_error() we have a single place to set an error flag (to
bail out and return an error on the next instruction) so that will be a
small change later when enough of the compiler bugs are sorted.

But re-arrange/cleanup the error/assert stuff so we at least get a dump
of the TGSI that triggered it.  So we see some useful output in piglit
logs.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2013-11-13 10:16:00 -05:00
Rob Clark
12da4c1a6a freedreno: fix segfault when no color buffer bound
Don't crash when no color buffer bound.  Something caught when starting
to run piglit, fixes a hanful of piglit tests.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2013-11-13 10:16:00 -05:00
Rob Clark
f3a7e28fe4 freedreno/a3xx/compiler: cat4 cannot use const reg as src
Category 4 instructions (rsq, rcp, sqrt, etc) seem to be unable to take
a const register as src.  In these cases we need to move the src to a
temporary gpr first.

This is the second case of such a restriction, where the instruction
encoding appears to support a const src, but in fact the hw appears to
ignore that bit.  So split things out into a helper that can be re-used
for any instructions which have this limitation.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2013-11-13 10:16:00 -05:00
Rob Clark
5394a872f3 freedreno/a3xx/compiler: use max_reg rather than file_count
Our current (rather naive) register assignment is based on mapping
different register files (INPUT, OUTPUT, TEMP, CONST, etc) based on the
max register index of the preceding file.  But in some cases, the lowest
used register in a file might not be zero.  In which case
file_count[file] != file_max[file] + 1.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2013-11-13 10:16:00 -05:00
Rob Clark
c833874386 freedreno/a3xx/compiler: handle saturate on dst
Sometimes things other than color dst need saturating, like if there is
a 'clamp(foo, 0.0, 1.0)'.  So for saturated dst add the extra
instructions to fix up dst.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2013-11-13 10:15:59 -05:00
Rob Clark
83e6532001 freedreno/a3xx/compiler: fix CMP
The 1st src to add.s needs (r) flag (repeat), otherwise it will end up:

  add.s dst.xyzw, tmp.xxxx -1

instead of:

  add.s dst.xyzw, tmp.xyzw, -1

Also, if we are using a temporary dst to avoid clobbering one of the src
registers, we actually need to use that as the dst for the sel
instruction.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2013-11-13 10:15:59 -05:00
Rob Clark
3da8868b5d freedreno/a3xx: some texture fixes
Stop hard coding bits that indicate texture type (2d/3d/cube/etc).

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2013-11-13 10:15:59 -05:00
Rob Clark
e1e9f69d3c freedreno: update register headers
resync w/ rnndb database

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2013-11-13 10:15:58 -05:00
Rob Clark
8b167d34be freedreno: add debug option to disable scissor optimization
Useful for testing and debugging.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2013-11-13 10:15:58 -05:00
Rob Clark
b2a32254d6 freedreno/a3xx: fix viewport on gmem->mem resolve
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2013-11-13 10:15:57 -05:00
Carl Worth
08d7c08512 docs: Add MD5 sums for the 9.2.3 release
We can do this now that the release tree has been tagged and tar files have
been generated.
2013-11-13 07:13:21 -08:00
Carl Worth
f4657c4e10 docs: Add releases notes for 9.2.3 release
Which cannot have the checksums yet, of course.
2013-11-13 07:08:37 -08:00
Carl Worth
a6252a56a5 Bump version to 9.2.3
In preparation for the 9.2.3 stable release.
2013-11-13 07:04:01 -08:00
Rob Clark
2d844be97f freedreno/a3xx: fix color inversion on mem->gmem restore
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2013-11-13 09:47:40 -05:00
Petr Sebor
cf33e6d85d meta: enable vertex attributes in the context of the newly created array object
Otherwise, the function would enable generic vertex attributes 0
and 1 of the array object it does not own. This was causing crashes
in Euro Truck Simulator 2, since the incorrectly enabled generic
attribute 0 in the foreign context got precedence before vertex
position attribute at later time, leading to NULL pointer dereference.

Cc: "9.2" <mesa-stable@lists.freedesktop.org>
Cc: "10.0" <mesa-stable@lists.freedesktop.org>

Signed-off-by: Petr Sebor <petr@scssoft.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
(cherry picked from commit f2b844f59d)
2013-11-12 16:48:00 -08:00
Brian Paul
69d5778b36 osmesa: fix broken triangle/line drawing when using float color buffer
Doesn't seem to help with bug 71363 but it fixed a failure I found in
my testing.

Cc: "9.2" <mesa-stable@lists.freedesktop.org>
Cc: "10.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit a66a008b17)
2013-11-12 16:47:50 -08:00
Carl Worth
9b8c5847e6 get-pick-list.sh: Onlly show commits specifically tagged for 9.2.
Now that the 10.0 branch has been created, we only consider patches for the
9.2 branch if the author specifically tags them for this branch.
2013-11-12 16:45:59 -08:00
Kenneth Graunke
6e491b875f i965: Also emit HiZ and Stencil packets when disabling depth on Gen6.
The normal drawing path does this, and it's necessary on Ivybridge,
so let's try it on Sandybridge too.  It's not explicitly documented
as necessary, but might help with hangs.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Xinkai Chen <yeled.nova@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Cc: "9.2" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 5563dfabc8)
2013-11-12 16:42:27 -08:00
Kenneth Graunke
57cd553eda i965: Also emit HIER_DEPTH and STENCIL packets when disabling depth.
From the documentation:
"[DevIVB] 3DSTATE_DEPTH_BUFFER must always be programmed along with the
 other Depth/Stencil state commands(i.e. 3DSTATE_CLEAR_PARAMS,
 3DSTATE_STENCIL_BUFFER, or 3DSTATE_HIER_DEPTH_BUFFER)."

We normally do this, but BLORP was failing to do so in the case where it
disables depth.

Not observed to fix anything yet.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Xinkai Chen <yeled.nova@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Cc: "9.2" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 29e5d5db51)
2013-11-12 16:42:04 -08:00
Kenneth Graunke
95a708abe6 i965: Move post-sync non-zero flush for 3DSTATE_MULTISAMPLE.
For some reason, we put the flush in the caller, rather than just before
emitting the packet.  This is more than a cosmetic problem: BLORP calls
gen6_emit_3dstate_multisample() directly, and so it missed the flush.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Xinkai Chen <yeled.nova@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Cc: "9.2" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 65b1f642ac)
2013-11-12 16:41:35 -08:00
Kenneth Graunke
8c2e3c8275 i965: Also guard 3DSTATE_DRAWING_RECTANGLE with a flush in blorp.
Non-pipelined commands need this flush.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Xinkai Chen <yeled.nova@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Cc: "9.2" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 10a918e52c)
2013-11-12 16:41:17 -08:00
Kenneth Graunke
81245daed3 i965: Emit post-sync non-zero flush before 3DSTATE_DRAWING_RECTANGLE.
This is another non-pipelined command that needs a flush on Sandybridge.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Xinkai Chen <yeled.nova@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Cc: "9.2" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 3aef1fefb4)
2013-11-12 16:41:02 -08:00
Kenneth Graunke
e5ed198f35 i965: Emit post-sync non-zero flush before 3DSTATE_GS_SVB_INDEX.
From the comments above intel_emit_post_sync_nonzero_flush:
"[DevSNB-C+{W/A}] Before any depth stall flush (including those
 produced by non-pipelined state commands), software needs to first
 send a PIPE_CONTROL with no bits set except Post-Sync Operation != 0."

This suggests that every non-pipelined (0x79xx) command needs a
post-sync non-zero flush before it.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Xinkai Chen <yeled.nova@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Cc: "9.2" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 436e815a25)
2013-11-12 16:40:38 -08:00
Daniel Vetter
52a6ebe200 i965: CS writes/reads should use I915_GEM_INSTRUCTION
Otherwise the gen6 w/a in the kernel won't kick in and the write will
land nowhere.

Inspired by a patch Ken pointed me at which had the same issue (but
isn't yet merged and also for a gen7+ feature). An audit of the entire
driver didn't reveal any other case than the one in in the write_reg
helper used by the gen6 queryobj code.

Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Tested-by: Xinkai Chen <yeled.nova@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Cc: "9.2" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 32a3f5f6d7)

Conflicts:
	src/mesa/drivers/dri/i965/gen6_queryobj.c
2013-11-12 16:40:16 -08:00
Brian Paul
5dc0d13e3d st/mesa: move out of memory check in st_draw_vbo()
Before we were only checking the st->vertex_array_out_of_memory flag
after updating array state.  But if there's two consecutive glDrawArrays
calls and the first one is skipped because of OOM, the second one should
be skipped too.

Cc: 9.2 <mesa-stable@lists.freedesktop.org>

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit d0eaf6752d)
2013-10-30 17:31:06 -07:00
Carl Worth
dbeb24c39b Remove error when calling glGenQueries/glDeleteQueries while a query is active
There is nothing in the OpenGL specification which prevents the user from
calling glGenQueries to generate a new query object while another object is
active. Neither is there anything in the Mesa implementation which prevents
this. So remove the INVALID_OPERATION errors in this case.

Similarly, it is explicitly allowed by the OpenGL specification to delete an
active query, so remove the assertion for that case, replacing it with the
necesssary state updates to end the query, (clear the bindpt pointer and call
into the driver's EndQuery hook).

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
Tested-by: Brian Paul <brianp@vmware.com>
(cherry picked from commit 29996e2199)
2013-10-30 17:31:06 -07:00
Carl Worth
621a461cd9 cherry-ignore: Update for newly-backported commit
This commit was recently backported by Marek, so we can drop the exception from cherry-ignore now.
2013-10-30 17:31:06 -07:00
Marek Olšák
259448d02f radeonsi: fix blitting the last 2 mipmap levels of compressed textures
This fixes compressedteximage piglit tests.

+10 piglits

Evergreen and Cayman have the same issue. R600 and R700 don't.

Cc: "9.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
(cherry picked from commit 57f38e9f92)

Conflicts:
	src/gallium/drivers/radeonsi/r600_resource.h
	src/gallium/drivers/radeonsi/si_state.c
2013-10-30 16:20:04 -07:00
Carl Worth
c8e0d10c0a cherry-ignore: Ignore another commit
This one is a bug fix for code that is not actually present in 9.2, (the code
being fixed was added in commit commit 079bdba05f ).
2013-10-28 09:56:34 -07:00
Carl Worth
26c599e00a cherry-ignore: Ignore two more patches.
One of these was recently backported, (the backported commit message doesn't
have the exact format expected by get-pick-list.sh, so we add it manually
here).

On the other, I haven't heard back from a couple of requests to the authors to
backport the patch to 9.2.
2013-10-28 09:21:05 -07:00
Eric Anholt
6f966b58a1 i965: Fix texture buffer rendering after a whole buffer replacement.
If glBufferData(), glBufferSubData(0, obj->Size), or similar happens, we
get a new drm_intel_bo for the buffer object, and thus need to re-upload
texture buffer state so we point at the new data.

Fixes the new piglit GL_ARB_texture_buffer_object/data-sync

Cc: "9.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
(cherry picked from commit c0a9436d19)
2013-10-25 17:19:13 -07:00
Scott Graham
6e557f03f3 mesa: fixes for MSVC 2013
Cc: "9.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
(cherry picked from commit dafa97fed9)
2013-10-25 17:18:37 -07:00
Kristian Høgsberg
7ab2b8c4c4 wayland: Don't rely on static variable for identifying wl_drm buffers
Now that libEGL has been fixed to not leak all kinds of symbols, gbm
links to its own copy of the libwayland-drm.a helper library.  That means
we can't rely on comparing the addresses of a static vtable symbol in that
library to determine if a wl_buffer is a wl_drm_buffer.  Instead, we
move the vtable into the wl_drm struct and use that for comparing.

Backported from 360a141f24.

https://bugs.freedesktop.org/show_bug.cgi?id=69437

Cc: 9.2 <mesa-stable@lists.freedesktop.org>
2013-10-24 14:00:40 -07:00