mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
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freedreno/a3xx/compiler: bit of re-arrange/cleanup
It seems there are a number of cases where instructions have limitations about taking reading src's from const register file, so make get_unconst() a bit easier to use. Signed-off-by: Rob Clark <robclark@freedesktop.org>
This commit is contained in:
Rob Clark
parent
c726a6a907
commit
ca5514b851
1 changed files with 71 additions and 61 deletions
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@ -91,6 +91,7 @@ struct fd3_compile_context {
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unsigned next_inloc;
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unsigned num_internal_temps;
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struct tgsi_src_register internal_temps[6];
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/* track registers which need to synchronize w/ "complex alu" cat3
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* instruction pipeline:
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@ -128,7 +129,7 @@ struct fd3_compile_context {
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* up the vector operation
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*/
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struct tgsi_dst_register tmp_dst;
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struct tgsi_src_register tmp_src;
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struct tgsi_src_register *tmp_src;
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};
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@ -309,11 +310,11 @@ src_from_dst(struct tgsi_src_register *src, struct tgsi_dst_register *dst)
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/* Get internal-temp src/dst to use for a sequence of instructions
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* generated by a single TGSI op.
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*/
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static void
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static struct tgsi_src_register *
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get_internal_temp(struct fd3_compile_context *ctx,
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struct tgsi_dst_register *tmp_dst,
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struct tgsi_src_register *tmp_src)
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struct tgsi_dst_register *tmp_dst)
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{
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struct tgsi_src_register *tmp_src;
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int n;
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tmp_dst->File = TGSI_FILE_TEMPORARY;
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@ -323,23 +324,28 @@ get_internal_temp(struct fd3_compile_context *ctx,
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/* assign next temporary: */
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n = ctx->num_internal_temps++;
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compile_assert(ctx, n < ARRAY_SIZE(ctx->internal_temps));
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tmp_src = &ctx->internal_temps[n];
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tmp_dst->Index = ctx->info.file_max[TGSI_FILE_TEMPORARY] + n + 1;
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src_from_dst(tmp_src, tmp_dst);
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return tmp_src;
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}
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/* same as get_internal_temp, but w/ src.xxxx (for instructions that
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* replicate their results)
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*/
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static void
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static struct tgsi_src_register *
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get_internal_temp_repl(struct fd3_compile_context *ctx,
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struct tgsi_dst_register *tmp_dst,
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struct tgsi_src_register *tmp_src)
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struct tgsi_dst_register *tmp_dst)
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{
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get_internal_temp(ctx, tmp_dst, tmp_src);
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struct tgsi_src_register *tmp_src =
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get_internal_temp(ctx, tmp_dst);
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tmp_src->SwizzleX = tmp_src->SwizzleY =
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tmp_src->SwizzleZ = tmp_src->SwizzleW = TGSI_SWIZZLE_X;
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return tmp_src;
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}
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static inline bool
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@ -349,6 +355,22 @@ is_const(struct tgsi_src_register *src)
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(src->File == TGSI_FILE_IMMEDIATE);
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}
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/* for instructions that cannot take a const register as src, if needed
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* generate a move to temporary gpr:
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*/
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static struct tgsi_src_register *
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get_unconst(struct fd3_compile_context *ctx, struct tgsi_src_register *src)
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{
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if (is_const(src)) {
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static struct tgsi_dst_register tmp_dst;
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struct tgsi_src_register *tmp_src =
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get_internal_temp(ctx, &tmp_dst);
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create_mov(ctx, &tmp_dst, src);
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src = tmp_src;
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}
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return src;
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}
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static void
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get_immediate(struct fd3_compile_context *ctx,
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struct tgsi_src_register *reg, uint32_t val)
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@ -396,27 +418,16 @@ get_immediate(struct fd3_compile_context *ctx,
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reg->SwizzleW = swiz2tgsi[swiz];
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}
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/* for instructions that cannot take a const register as src, if needed
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* generate a move to temporary gpr:
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*/
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static struct tgsi_src_register *
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get_unconst(struct fd3_compile_context *ctx, struct tgsi_src_register *src,
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struct tgsi_src_register *tmp_src)
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static type_t
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get_ftype(struct fd3_compile_context *ctx)
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{
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static struct tgsi_dst_register tmp_dst;
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if ((src->File == TGSI_FILE_CONSTANT) ||
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(src->File == TGSI_FILE_IMMEDIATE)) {
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get_internal_temp(ctx, &tmp_dst, tmp_src);
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create_mov(ctx, &tmp_dst, src);
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src = tmp_src;
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}
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return src;
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return ctx->so->half_precision ? TYPE_F16 : TYPE_F32;
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}
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static type_t
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get_type(struct fd3_compile_context *ctx)
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get_utype(struct fd3_compile_context *ctx)
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{
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return ctx->so->half_precision ? TYPE_F16 : TYPE_F32;
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return ctx->so->half_precision ? TYPE_U16 : TYPE_U32;
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}
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static unsigned
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@ -436,7 +447,7 @@ static void
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create_mov(struct fd3_compile_context *ctx, struct tgsi_dst_register *dst,
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struct tgsi_src_register *src)
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{
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type_t type_mov = get_type(ctx);
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type_t type_mov = get_ftype(ctx);
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unsigned i;
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for (i = 0; i < 4; i++) {
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@ -492,7 +503,7 @@ get_dst(struct fd3_compile_context *ctx, struct tgsi_full_instruction *inst)
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for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
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struct tgsi_src_register *src = &inst->Src[i].Register;
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if ((src->File == dst->File) && (src->Index == dst->Index)) {
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get_internal_temp(ctx, &ctx->tmp_dst, &ctx->tmp_src);
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ctx->tmp_src = get_internal_temp(ctx, &ctx->tmp_dst);
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ctx->tmp_dst.WriteMask = dst->WriteMask;
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dst = &ctx->tmp_dst;
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break;
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@ -507,7 +518,7 @@ put_dst(struct fd3_compile_context *ctx, struct tgsi_full_instruction *inst,
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{
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/* if necessary, add mov back into original dst: */
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if (dst != &inst->Dst[0].Register) {
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create_mov(ctx, &inst->Dst[0].Register, &ctx->tmp_src);
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create_mov(ctx, &inst->Dst[0].Register, ctx->tmp_src);
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}
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}
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@ -580,7 +591,7 @@ trans_dotp(const struct instr_translater *t,
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{
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struct ir3_instruction *instr;
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struct tgsi_dst_register tmp_dst;
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struct tgsi_src_register tmp_src;
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struct tgsi_src_register *tmp_src;
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struct tgsi_dst_register *dst = &inst->Dst[0].Register;
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struct tgsi_src_register *src0 = &inst->Src[0].Register;
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struct tgsi_src_register *src1 = &inst->Src[1].Register;
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@ -590,7 +601,7 @@ trans_dotp(const struct instr_translater *t,
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unsigned n = t->arg; /* number of components */
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unsigned i;
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get_internal_temp_repl(ctx, &tmp_dst, &tmp_src);
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tmp_src = get_internal_temp_repl(ctx, &tmp_dst);
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/* Blob compiler never seems to use a const in src1 position for
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* mad.*, although there does seem (according to disassembler
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@ -609,7 +620,7 @@ trans_dotp(const struct instr_translater *t,
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* because after that point we no longer need tmp.x:
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*/
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create_mov(ctx, &tmp_dst, src1);
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src1 = &tmp_src;
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src1 = tmp_src;
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}
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instr = ir3_instr_create(ctx->ir, 2, OPC_MUL_F);
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@ -624,7 +635,7 @@ trans_dotp(const struct instr_translater *t,
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add_dst_reg(ctx, instr, &tmp_dst, 0);
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add_src_reg(ctx, instr, src0, swiz0[i]);
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add_src_reg(ctx, instr, src1, swiz1[i]);
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add_src_reg(ctx, instr, &tmp_src, 0);
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add_src_reg(ctx, instr, tmp_src, 0);
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}
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/* DPH(a,b) = (a.x * b.x) + (a.y * b.y) + (a.z * b.z) + b.w */
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@ -634,7 +645,7 @@ trans_dotp(const struct instr_translater *t,
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instr = ir3_instr_create(ctx->ir, 2, OPC_ADD_F);
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add_dst_reg(ctx, instr, &tmp_dst, 0);
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add_src_reg(ctx, instr, src1, swiz1[i]);
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add_src_reg(ctx, instr, &tmp_src, 0);
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add_src_reg(ctx, instr, tmp_src, 0);
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n++;
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}
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@ -646,7 +657,7 @@ trans_dotp(const struct instr_translater *t,
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ir3_instr_create(ctx->ir, 0, OPC_NOP);
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}
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create_mov(ctx, dst, &tmp_src);
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create_mov(ctx, dst, tmp_src);
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}
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/* LRP(a,b,c) = (a * b) + ((1 - a) * c) */
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@ -657,11 +668,11 @@ trans_lrp(const struct instr_translater *t,
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{
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struct ir3_instruction *instr;
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struct tgsi_dst_register tmp_dst1, tmp_dst2;
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struct tgsi_src_register tmp_src1, tmp_src2;
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struct tgsi_src_register *tmp_src1, *tmp_src2;
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struct tgsi_src_register tmp_const;
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get_internal_temp(ctx, &tmp_dst1, &tmp_src1);
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get_internal_temp(ctx, &tmp_dst2, &tmp_src2);
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tmp_src1 = get_internal_temp(ctx, &tmp_dst1);
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tmp_src2 = get_internal_temp(ctx, &tmp_dst2);
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get_immediate(ctx, &tmp_const, fui(1.0));
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@ -680,14 +691,14 @@ trans_lrp(const struct instr_translater *t,
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/* tmp2 = tmp2 * c */
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instr = ir3_instr_create(ctx->ir, 2, OPC_MUL_F);
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vectorize(ctx, instr, &tmp_dst2, 2,
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&tmp_src2, 0,
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tmp_src2, 0,
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&inst->Src[2].Register, 0);
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/* dst = tmp1 + tmp2 */
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instr = ir3_instr_create(ctx->ir, 2, OPC_ADD_F);
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vectorize(ctx, instr, &inst->Dst[0].Register, 2,
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&tmp_src1, 0,
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&tmp_src2, 0);
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tmp_src1, 0,
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tmp_src2, 0);
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}
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/* FRC(x) = x - FLOOR(x) */
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@ -698,9 +709,9 @@ trans_frac(const struct instr_translater *t,
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{
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struct ir3_instruction *instr;
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struct tgsi_dst_register tmp_dst;
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struct tgsi_src_register tmp_src;
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struct tgsi_src_register *tmp_src;
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get_internal_temp(ctx, &tmp_dst, &tmp_src);
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tmp_src = get_internal_temp(ctx, &tmp_dst);
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/* tmp = FLOOR(x) */
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instr = ir3_instr_create(ctx->ir, 2, OPC_FLOOR_F);
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@ -711,7 +722,7 @@ trans_frac(const struct instr_translater *t,
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instr = ir3_instr_create(ctx->ir, 2, OPC_ADD_F);
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vectorize(ctx, instr, &inst->Dst[0].Register, 2,
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&inst->Src[0].Register, 0,
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&tmp_src, IR3_REG_NEGATE);
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tmp_src, IR3_REG_NEGATE);
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}
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/* POW(a,b) = EXP2(b * LOG2(a)) */
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@ -723,12 +734,12 @@ trans_pow(const struct instr_translater *t,
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struct ir3_instruction *instr;
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struct ir3_register *r;
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struct tgsi_dst_register tmp_dst;
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struct tgsi_src_register tmp_src;
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struct tgsi_src_register *tmp_src;
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struct tgsi_dst_register *dst = &inst->Dst[0].Register;
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struct tgsi_src_register *src0 = &inst->Src[0].Register;
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struct tgsi_src_register *src1 = &inst->Src[1].Register;
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get_internal_temp_repl(ctx, &tmp_dst, &tmp_src);
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tmp_src = get_internal_temp_repl(ctx, &tmp_dst);
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/* log2 Rtmp, Rsrc0 */
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ir3_instr_create(ctx->ir, 0, OPC_NOP)->repeat = 5;
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@ -740,7 +751,7 @@ trans_pow(const struct instr_translater *t,
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/* mul.f Rtmp, Rtmp, Rsrc1 */
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instr = ir3_instr_create(ctx->ir, 2, OPC_MUL_F);
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add_dst_reg(ctx, instr, &tmp_dst, 0);
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add_src_reg(ctx, instr, &tmp_src, 0);
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add_src_reg(ctx, instr, tmp_src, 0);
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add_src_reg(ctx, instr, src1, src1->SwizzleX);
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/* blob compiler seems to ensure there are at least 6 instructions
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@ -752,10 +763,10 @@ trans_pow(const struct instr_translater *t,
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/* exp2 Rdst, Rtmp */
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instr = ir3_instr_create(ctx->ir, 4, OPC_EXP2);
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r = add_dst_reg(ctx, instr, &tmp_dst, 0);
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add_src_reg(ctx, instr, &tmp_src, 0);
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add_src_reg(ctx, instr, tmp_src, 0);
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regmask_set(ctx->needs_ss, r);
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create_mov(ctx, dst, &tmp_src);
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create_mov(ctx, dst, tmp_src);
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}
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/* texture fetch/sample instructions: */
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@ -766,8 +777,6 @@ trans_samp(const struct instr_translater *t,
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{
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struct ir3_register *r;
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struct ir3_instruction *instr;
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struct tgsi_dst_register tmp_dst;
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struct tgsi_src_register tmp_src;
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struct tgsi_src_register *coord = &inst->Src[0].Register;
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struct tgsi_src_register *samp = &inst->Src[1].Register;
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unsigned tex = inst->Texture.Texture;
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@ -802,10 +811,13 @@ trans_samp(const struct instr_translater *t,
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*/
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for (i = 1; (i < 4) && (order[i] >= 0); i++) {
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if (src_swiz(coord, i) != (src_swiz(coord, 0) + order[i])) {
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type_t type_mov = get_type(ctx);
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struct tgsi_dst_register tmp_dst;
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struct tgsi_src_register *tmp_src;
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type_t type_mov = get_ftype(ctx);
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/* need to move things around: */
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get_internal_temp(ctx, &tmp_dst, &tmp_src);
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tmp_src = get_internal_temp(ctx, &tmp_dst);
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for (j = 0; (j < 4) && (order[j] >= 0); j++) {
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instr = ir3_instr_create(ctx->ir, 1, 0);
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@ -816,7 +828,7 @@ trans_samp(const struct instr_translater *t,
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src_swiz(coord, order[j]));
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}
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coord = &tmp_src;
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coord = tmp_src;
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if (j < 4)
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ir3_instr_create(ctx->ir, 0, OPC_NOP)->repeat = 4 - j - 1;
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@ -826,7 +838,7 @@ trans_samp(const struct instr_translater *t,
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}
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instr = ir3_instr_create(ctx->ir, 5, t->opc);
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instr->cat5.type = get_type(ctx);
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instr->cat5.type = get_ftype(ctx);
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instr->cat5.samp = samp->Index;
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instr->cat5.tex = samp->Index;
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instr->flags |= flags;
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@ -847,12 +859,12 @@ trans_cmp(const struct instr_translater *t,
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{
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struct ir3_instruction *instr;
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struct tgsi_dst_register tmp_dst;
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struct tgsi_src_register tmp_src;
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struct tgsi_src_register *tmp_src;
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struct tgsi_src_register constval;
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/* final instruction uses original src1 and src2, so we need get_dst() */
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struct tgsi_dst_register *dst = get_dst(ctx, inst);
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get_internal_temp(ctx, &tmp_dst, &tmp_src);
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tmp_src = get_internal_temp(ctx, &tmp_dst);
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/* cmps.f.ge tmp, src0, 0.0 */
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instr = ir3_instr_create(ctx->ir, 2, OPC_CMPS_F);
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@ -866,7 +878,7 @@ trans_cmp(const struct instr_translater *t,
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instr = ir3_instr_create(ctx->ir, 2, OPC_ADD_S);
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instr->repeat = 3;
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add_dst_reg(ctx, instr, &tmp_dst, 0);
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add_src_reg(ctx, instr, &tmp_src, 0)->flags |= IR3_REG_R;
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add_src_reg(ctx, instr, tmp_src, 0)->flags |= IR3_REG_R;
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ir3_reg_create(instr, 0, IR3_REG_IMMED)->iim_val = -1;
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/* sel.{f32,f16} dst, src2, tmp, src1 */
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@ -874,7 +886,7 @@ trans_cmp(const struct instr_translater *t,
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OPC_SEL_F16 : OPC_SEL_F32);
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vectorize(ctx, instr, dst, 3,
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&inst->Src[2].Register, 0,
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&tmp_src, 0,
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tmp_src, 0,
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&inst->Src[1].Register, 0);
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put_dst(ctx, inst, dst);
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@ -1066,7 +1078,6 @@ instr_cat3(const struct instr_translater *t,
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{
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struct tgsi_dst_register *dst = get_dst(ctx, inst);
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struct tgsi_src_register *src1;
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struct tgsi_src_register tmp_src;
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struct ir3_instruction *instr;
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/* Blob compiler never seems to use a const in src1 position..
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@ -1075,7 +1086,7 @@ instr_cat3(const struct instr_translater *t,
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* const. Not sure if this is a hw bug, or simply that the
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* disassembler lies.
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*/
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src1 = get_unconst(ctx, &inst->Src[1].Register, &tmp_src);
|
||||
src1 = get_unconst(ctx, &inst->Src[1].Register);
|
||||
|
||||
instr = ir3_instr_create(ctx->ir, 3,
|
||||
ctx->so->half_precision ? t->hopc : t->opc);
|
||||
|
|
@ -1093,11 +1104,10 @@ instr_cat4(const struct instr_translater *t,
|
|||
{
|
||||
struct tgsi_dst_register *dst = get_dst(ctx, inst);
|
||||
struct tgsi_src_register *src;
|
||||
struct tgsi_src_register tmp_src;
|
||||
struct ir3_instruction *instr;
|
||||
|
||||
/* seems like blob compiler avoids const as src.. */
|
||||
src = get_unconst(ctx, &inst->Src[0].Register, &tmp_src);
|
||||
src = get_unconst(ctx, &inst->Src[0].Register);
|
||||
|
||||
ir3_instr_create(ctx->ir, 0, OPC_NOP)->repeat = 5;
|
||||
instr = ir3_instr_create(ctx->ir, 4, t->opc);
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue