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i965: Emit post-sync non-zero flush before 3DSTATE_DRAWING_RECTANGLE.

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This is another non-pipelined command that needs a flush on Sandybridge.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Xinkai Chen <yeled.nova@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Cc: "9.2" <mesa-stable@lists.freedesktop.org>
This commit is contained in:
Kenneth Graunke 2013-10-24 00:36:42 -07:00
parent 436e815a25
commit 3aef1fefb4
1 changed files with 4 additions and 0 deletions
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4
src/mesa/drivers/dri/i965/brw_misc_state.c
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@ -48,6 +48,10 @@ static void upload_drawing_rect(struct brw_context *brw)
{
struct gl_context *ctx = &brw->ctx;
/* 3DSTATE_DRAWING_RECTANGLE is non-pipelined. */
if (brw->gen == 6)
intel_emit_post_sync_nonzero_flush(brw);
BEGIN_BATCH(4);
OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE << 16 | (4 - 2));
OUT_BATCH(0); /* xmin, ymin */