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freedreno/a3xx/compiler: better const handling
Seems like most/all instructions have some restrictions about const src registers. In seems like the 2 src (cat2) instructions can take at most one const, and the 3 src (cat3) instructions can take at most one const in the first 2 arguments. And so on. Handle this properly now. Signed-off-by: Rob Clark <robclark@freedesktop.org>
This commit is contained in:
Rob Clark
parent
0b2c5119cb
commit
f1998c8aa7
1 changed files with 121 additions and 90 deletions
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@ -355,20 +355,47 @@ is_const(struct tgsi_src_register *src)
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(src->File == TGSI_FILE_IMMEDIATE);
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}
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static type_t
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get_ftype(struct fd3_compile_context *ctx)
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{
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return ctx->so->half_precision ? TYPE_F16 : TYPE_F32;
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}
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static type_t
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get_utype(struct fd3_compile_context *ctx)
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{
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return ctx->so->half_precision ? TYPE_U16 : TYPE_U32;
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}
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static unsigned
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src_swiz(struct tgsi_src_register *src, int chan)
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{
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switch (chan) {
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case 0: return src->SwizzleX;
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case 1: return src->SwizzleY;
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case 2: return src->SwizzleZ;
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case 3: return src->SwizzleW;
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}
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assert(0);
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return 0;
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}
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/* for instructions that cannot take a const register as src, if needed
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* generate a move to temporary gpr:
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*/
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static struct tgsi_src_register *
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get_unconst(struct fd3_compile_context *ctx, struct tgsi_src_register *src)
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{
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if (is_const(src)) {
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static struct tgsi_dst_register tmp_dst;
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struct tgsi_src_register *tmp_src =
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get_internal_temp(ctx, &tmp_dst);
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create_mov(ctx, &tmp_dst, src);
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src = tmp_src;
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}
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return src;
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struct tgsi_dst_register tmp_dst;
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struct tgsi_src_register *tmp_src;
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compile_assert(ctx, is_const(src));
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tmp_src = get_internal_temp(ctx, &tmp_dst);
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create_mov(ctx, &tmp_dst, src);
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return tmp_src;
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}
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static void
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@ -418,31 +445,6 @@ get_immediate(struct fd3_compile_context *ctx,
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reg->SwizzleW = swiz2tgsi[swiz];
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}
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static type_t
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get_ftype(struct fd3_compile_context *ctx)
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{
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return ctx->so->half_precision ? TYPE_F16 : TYPE_F32;
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}
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static type_t
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get_utype(struct fd3_compile_context *ctx)
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{
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return ctx->so->half_precision ? TYPE_U16 : TYPE_U32;
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}
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static unsigned
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src_swiz(struct tgsi_src_register *src, int chan)
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{
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switch (chan) {
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case 0: return src->SwizzleX;
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case 1: return src->SwizzleY;
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case 2: return src->SwizzleZ;
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case 3: return src->SwizzleW;
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}
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assert(0);
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return 0;
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}
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static void
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create_mov(struct fd3_compile_context *ctx, struct tgsi_dst_register *dst,
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struct tgsi_src_register *src)
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@ -463,7 +465,6 @@ create_mov(struct fd3_compile_context *ctx, struct tgsi_dst_register *dst,
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ir3_instr_create(ctx->ir, 0, OPC_NOP);
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}
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}
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}
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static void
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@ -584,6 +585,15 @@ vectorize(struct fd3_compile_context *ctx, struct ir3_instruction *instr,
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* native instructions:
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*/
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static inline void
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get_swiz(unsigned *swiz, struct tgsi_src_register *src)
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{
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swiz[0] = src->SwizzleX;
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swiz[1] = src->SwizzleY;
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swiz[2] = src->SwizzleZ;
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swiz[3] = src->SwizzleW;
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}
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static void
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trans_dotp(const struct instr_translater *t,
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struct fd3_compile_context *ctx,
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@ -595,34 +605,31 @@ trans_dotp(const struct instr_translater *t,
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struct tgsi_dst_register *dst = &inst->Dst[0].Register;
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struct tgsi_src_register *src0 = &inst->Src[0].Register;
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struct tgsi_src_register *src1 = &inst->Src[1].Register;
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unsigned swiz0[] = { src0->SwizzleX, src0->SwizzleY, src0->SwizzleZ, src0->SwizzleW };
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unsigned swiz1[] = { src1->SwizzleX, src1->SwizzleY, src1->SwizzleZ, src1->SwizzleW };
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unsigned swiz0[4];
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unsigned swiz1[4];
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opc_t opc_mad = ctx->so->half_precision ? OPC_MAD_F16 : OPC_MAD_F32;
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unsigned n = t->arg; /* number of components */
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unsigned i;
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unsigned i, swapped = 0;
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tmp_src = get_internal_temp_repl(ctx, &tmp_dst);
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/* Blob compiler never seems to use a const in src1 position for
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* mad.*, although there does seem (according to disassembler
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* hidden in libllvm-a3xx.so) to be a bit to indicate that src1
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* is a const. Not sure if this is a hw bug, or simply that the
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* disassembler lies.
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/* in particular, can't handle const for src1 for cat3/mad:
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*/
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if (is_const(src1)) {
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/* the mov to tmp unswizzles src1, so now we have tmp.xyzw:
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*/
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for (i = 0; i < 4; i++)
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swiz1[i] = i;
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/* the first mul.f will clobber tmp.x, but that is ok
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* because after that point we no longer need tmp.x:
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*/
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create_mov(ctx, &tmp_dst, src1);
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src1 = tmp_src;
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if (!is_const(src0)) {
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struct tgsi_src_register *tmp;
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tmp = src0;
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src0 = src1;
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src1 = tmp;
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swapped = 1;
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} else {
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src0 = get_unconst(ctx, src0);
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}
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}
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get_swiz(swiz0, src0);
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get_swiz(swiz1, src1);
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instr = ir3_instr_create(ctx->ir, 2, OPC_MUL_F);
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add_dst_reg(ctx, instr, &tmp_dst, 0);
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add_src_reg(ctx, instr, src0, swiz0[0]);
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@ -640,22 +647,20 @@ trans_dotp(const struct instr_translater *t,
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/* DPH(a,b) = (a.x * b.x) + (a.y * b.y) + (a.z * b.z) + b.w */
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if (t->tgsi_opc == TGSI_OPCODE_DPH) {
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ir3_instr_create(ctx->ir, 0, OPC_NOP);
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ir3_instr_create(ctx->ir, 0, OPC_NOP)->repeat = 1;
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instr = ir3_instr_create(ctx->ir, 2, OPC_ADD_F);
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add_dst_reg(ctx, instr, &tmp_dst, 0);
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add_src_reg(ctx, instr, src1, swiz1[i]);
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if (swapped)
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add_src_reg(ctx, instr, src0, swiz0[i]);
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else
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add_src_reg(ctx, instr, src1, swiz1[i]);
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add_src_reg(ctx, instr, tmp_src, 0);
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n++;
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}
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ir3_instr_create(ctx->ir, 0, OPC_NOP);
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/* pad out to multiple of 4 scalar instructions: */
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for (i = 2 * n; i % 4; i++) {
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ir3_instr_create(ctx->ir, 0, OPC_NOP);
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}
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ir3_instr_create(ctx->ir, 0, OPC_NOP)->repeat = 2;
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create_mov(ctx, dst, tmp_src);
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}
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@ -670,6 +675,11 @@ trans_lrp(const struct instr_translater *t,
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struct tgsi_dst_register tmp_dst1, tmp_dst2;
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struct tgsi_src_register *tmp_src1, *tmp_src2;
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struct tgsi_src_register tmp_const;
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struct tgsi_src_register *src0 = &inst->Src[0].Register;
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struct tgsi_src_register *src1 = &inst->Src[1].Register;
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if (is_const(src0) && is_const(src1))
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src0 = get_unconst(ctx, src0);
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tmp_src1 = get_internal_temp(ctx, &tmp_dst1);
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tmp_src2 = get_internal_temp(ctx, &tmp_dst2);
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@ -678,15 +688,12 @@ trans_lrp(const struct instr_translater *t,
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/* tmp1 = (a * b) */
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instr = ir3_instr_create(ctx->ir, 2, OPC_MUL_F);
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vectorize(ctx, instr, &tmp_dst1, 2,
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&inst->Src[0].Register, 0,
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&inst->Src[1].Register, 0);
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vectorize(ctx, instr, &tmp_dst1, 2, src0, 0, src1, 0);
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/* tmp2 = (1 - a) */
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instr = ir3_instr_create(ctx->ir, 2, OPC_ADD_F);
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vectorize(ctx, instr, &tmp_dst2, 2,
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&tmp_const, 0,
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&inst->Src[0].Register, IR3_REG_NEGATE);
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vectorize(ctx, instr, &tmp_dst2, 2, &tmp_const, 0,
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src0, IR3_REG_NEGATE);
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/* tmp2 = tmp2 * c */
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instr = ir3_instr_create(ctx->ir, 2, OPC_MUL_F);
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@ -930,10 +937,6 @@ trans_cmp(const struct instr_translater *t,
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return;
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}
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/* NOTE: seems blob compiler will move a const to a gpr if both
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* src args to cmps.f are const. Need to check if this applies
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* to other instructions..
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*/
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if (is_const(a0) && is_const(a1))
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a0 = get_unconst(ctx, a0);
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@ -1041,6 +1044,9 @@ trans_if(const struct instr_translater *t,
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get_immediate(ctx, &constval, fui(0.0));
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if (is_const(src))
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src = get_unconst(ctx, src);
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instr = ir3_instr_create(ctx->ir, 2, OPC_CMPS_F);
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ir3_reg_create(instr, regid(REG_P0, 0), 0);
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add_src_reg(ctx, instr, src, src->SwizzleX);
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@ -1122,11 +1128,11 @@ instr_cat2(const struct instr_translater *t,
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struct tgsi_full_instruction *inst)
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{
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struct tgsi_dst_register *dst = get_dst(ctx, inst);
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struct tgsi_src_register *src0 = &inst->Src[0].Register;
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struct tgsi_src_register *src1 = &inst->Src[1].Register;
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struct ir3_instruction *instr;
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unsigned src0_flags = 0;
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instr = ir3_instr_create(ctx->ir, 2, t->opc);
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switch (t->tgsi_opc) {
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case TGSI_OPCODE_ABS:
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src0_flags = IR3_REG_ABS;
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@ -1149,41 +1155,65 @@ instr_cat2(const struct instr_translater *t,
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case OPC_SETRM:
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case OPC_CBITS_B:
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/* these only have one src reg */
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vectorize(ctx, instr, dst, 1,
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&inst->Src[0].Register, src0_flags);
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instr = ir3_instr_create(ctx->ir, 2, t->opc);
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vectorize(ctx, instr, dst, 1, src0, src0_flags);
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break;
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default:
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vectorize(ctx, instr, dst, 2,
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&inst->Src[0].Register, src0_flags,
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&inst->Src[1].Register, 0);
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if (is_const(src0) && is_const(src1))
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src0 = get_unconst(ctx, src0);
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instr = ir3_instr_create(ctx->ir, 2, t->opc);
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vectorize(ctx, instr, dst, 2, src0, src0_flags, src1, 0);
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break;
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}
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put_dst(ctx, inst, dst);
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}
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static bool is_mad(opc_t opc)
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{
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switch (opc) {
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case OPC_MAD_U16:
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case OPC_MADSH_U16:
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case OPC_MAD_S16:
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case OPC_MADSH_M16:
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case OPC_MAD_U24:
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case OPC_MAD_S24:
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case OPC_MAD_F16:
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case OPC_MAD_F32:
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return true;
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default:
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return false;
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}
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}
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static void
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instr_cat3(const struct instr_translater *t,
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struct fd3_compile_context *ctx,
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struct tgsi_full_instruction *inst)
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{
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struct tgsi_dst_register *dst = get_dst(ctx, inst);
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struct tgsi_src_register *src1;
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struct tgsi_src_register *src0 = &inst->Src[0].Register;
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struct tgsi_src_register *src1 = &inst->Src[1].Register;
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struct ir3_instruction *instr;
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/* Blob compiler never seems to use a const in src1 position..
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* although there does seem (according to disassembler hidden
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* in libllvm-a3xx.so) to be a bit to indicate that src1 is a
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* const. Not sure if this is a hw bug, or simply that the
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* disassembler lies.
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/* in particular, can't handle const for src1 for cat3..
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* for mad, we can swap first two src's if needed:
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*/
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src1 = get_unconst(ctx, &inst->Src[1].Register);
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if (is_const(src1)) {
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if (is_mad(t->opc) && !is_const(src0)) {
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struct tgsi_src_register *tmp;
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tmp = src0;
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src0 = src1;
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src1 = tmp;
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} else {
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src0 = get_unconst(ctx, src0);
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}
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}
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instr = ir3_instr_create(ctx->ir, 3,
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ctx->so->half_precision ? t->hopc : t->opc);
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vectorize(ctx, instr, dst, 3,
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&inst->Src[0].Register, 0,
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src1, 0,
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vectorize(ctx, instr, dst, 3, src0, 0, src1, 0,
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&inst->Src[2].Register, 0);
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put_dst(ctx, inst, dst);
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}
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@ -1194,11 +1224,12 @@ instr_cat4(const struct instr_translater *t,
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struct tgsi_full_instruction *inst)
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{
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struct tgsi_dst_register *dst = get_dst(ctx, inst);
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struct tgsi_src_register *src;
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struct tgsi_src_register *src = &inst->Src[0].Register;
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struct ir3_instruction *instr;
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/* seems like blob compiler avoids const as src.. */
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src = get_unconst(ctx, &inst->Src[0].Register);
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if (is_const(src))
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src = get_unconst(ctx, src);
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ir3_instr_create(ctx->ir, 0, OPC_NOP)->repeat = 5;
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instr = ir3_instr_create(ctx->ir, 4, t->opc);
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