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i965: Emit post-sync non-zero flush before 3DSTATE_GS_SVB_INDEX.

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From the comments above intel_emit_post_sync_nonzero_flush:
"[DevSNB-C+{W/A}] Before any depth stall flush (including those
 produced by non-pipelined state commands), software needs to first
 send a PIPE_CONTROL with no bits set except Post-Sync Operation != 0."

This suggests that every non-pipelined (0x79xx) command needs a
post-sync non-zero flush before it.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Xinkai Chen <yeled.nova@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Cc: "9.2" <mesa-stable@lists.freedesktop.org>
This commit is contained in:
Kenneth Graunke 2013-10-24 00:32:52 -07:00
parent 32a3f5f6d7
commit 436e815a25
1 changed files with 3 additions and 0 deletions
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3
src/mesa/drivers/dri/i965/gen6_sol.c
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@ -153,6 +153,9 @@ brw_begin_transform_feedback(struct gl_context *ctx, GLenum mode,
= _mesa_compute_max_transform_feedback_vertices(xfb_obj,
linked_xfb_info);
/* 3DSTATE_GS_SVB_INDEX is non-pipelined. */
intel_emit_post_sync_nonzero_flush(brw);
/* Initialize the SVBI 0 register to zero and set the maximum index. */
BEGIN_BATCH(4);
OUT_BATCH(_3DSTATE_GS_SVB_INDEX << 16 | (4 - 2));