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Yonggang Luo
9649eee307 meson: Use /Zc:enumTypes enables C++ conforming enum underlying type and enumerator type deduction
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The detail is at https://learn.microsoft.com/en-us/cpp/build/reference/zc-enumtypes?view=msvc-170

For example:

enum Enum {
    A = 'A',
    B = sizeof(A)
};

static_assert(B == 1); // previously failed, now succeeds under /Zc:enumTypes

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38639>
 2025-12-08 22:47:13 +00:00
Rob Clark
6e3598177b freedreno/common: Add A840 and X2-85 
Add support for A840 and X2-85.  Despite slice count, differences in
memory bus and clks, they are architecturally similar from the PoV of
the UMD.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:12:12 +00:00
Rob Clark
11364f4ee2 freedreno: gen8 support 
Enable gen8 support.  Sysmem, gmem, and binning work.  DEQP gles2/3/31
tests are passing.

LRZ is not supported yet, and will follow later.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:12:12 +00:00
Rob Clark
469a19f66b freedreno/computerator: gen8 support 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:12:12 +00:00
Rob Clark
46dd4b166e freedreno/a6xx: Fix VSC_BIN_SIZE for gen8 
It was missed that this register changed for larger bin sizes.   Use a
common bitset for all related gen8 regs, and change the field names for
earlier gens to match so the generated register packers dtrt.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:12:12 +00:00
Rob Clark
237e93aa45 freedreno/a6xx: Add gen8 query support 
The RBBM_PIPESTAT_x regs moved around.  Re-work how we figure out the
appropriate reg offset to take this into account by using the templated
reg packers.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:12:12 +00:00
Rob Clark
e15ac3b043 freedreno/a6xx: Drop log_pipeline_stats() 
This was useful when we didn't have docs and had to figure out which
counter was which.  That is no longer an issue.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:12:12 +00:00
Rob Clark
a818287fd6 freedreno/registers: gen8 support 
Co-developed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:12:11 +00:00
Rob Clark
6c39336f2f freedreno/registers: More gen8 prep 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:12:11 +00:00
Rob Clark
01041c858e freedreno/a6xx: Handle tess_bo size differences for gen8 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:12:10 +00:00
Rob Clark
222c005c01 freedreno/fdl: Fix gen8 buffer depth 
Seems we need to program it to 1, otherwise all ssbo writes (and reads?)
end up in index 0.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:12:10 +00:00
Rob Clark
5310672706 freedreno/fdl: Fix gen8 TEX_LINE_OFFSET 
It is in units of bits.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:12:10 +00:00
Rob Clark
4f6076f531 freedreno/registers: Add TPL1_MODE_CNTL bitfields 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:12:09 +00:00
Rob Clark
be6c181ae6 freedreno/registers: Fix gen8 UBWC array pitch 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:12:08 +00:00
Rob Clark
5c98f110da ir3: Add new cat3 instructions 
b13 encodes alternate opcode meanings for new instructions with
otherwise the same encoding (ie. src precision implied by opc).

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:12:08 +00:00
Rob Clark
aadd1dabde ir3: dp2acc is removed in gen8 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:12:08 +00:00
Rob Clark
9d3102048e ir3: Add new cat2 instructions 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:12:07 +00:00
Rob Clark
937625c391 ir3: Fix gen8 ldc encoding 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:12:06 +00:00
Rob Clark
e53c605adf ir3: Add mova.r encoding 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:12:06 +00:00
Rob Clark
688d62381c ir3: Use ldc.u in preamble 
r63.u isn't a shared reg, so we weren't setting the .u bit on ldc.  But
in a preamble, we should be.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:12:05 +00:00
Rob Clark
d146a31ee1 ir3: Add mova .u bit 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:12:05 +00:00
Rob Clark
4bc01d11b0 ir3: Add cat3 flut src encoding 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:12:05 +00:00
Rob Clark
c35b5f9726 ir3: Add cat3 alt immed encoding 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:12:04 +00:00
Rob Clark
1c7c4b4807 ir3: Add cat1 (sat) bit 
Appears to be present at least as far back as gen7.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:12:04 +00:00
Rob Clark
69e0536203 ir3: Add (eostsc) 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:12:03 +00:00
Rob Clark
fa5be473b8 ir3: Add disasm test macro for gen8 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:12:03 +00:00
Rob Clark
189e494249 ir3: Add (sy) before end of preamble when necessary 
We need to ensure GPR writes completes before the end of the preamble
to avoid writes landing after another preamble has already started.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:12:02 +00:00
Rob Clark
a48e4b8340 ir3: Extract out helper for nop flags 
Extract out a helper to add a flag to a nop, potentially re-using a
previous nop where possible.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:12:01 +00:00
Rob Clark
d1df3b4e39 ir3: Limit CS lock/unlock quirk 
We don't need this universally for everything >= gen7.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:12:01 +00:00
Rob Clark
e00bff2513 ir3: Fix cat3 latency 
The rule about only needing two cycles for 3rd src of cat3 instructions
only applies to variants of mad.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:12:01 +00:00
Rob Clark
02a4cc622d ir3: Fix gen8 instruction timings 
non_alu is still 6.  But AFAICT none of this changes since a7xx so these
were probably wrong on a7xx as well.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:12:01 +00:00
Rob Clark
3e7f200e1f ir3: Skip non-bindless ldc warmups 
Non bindless UBOs are pushed in cmdstream, so warmup instructions should
be unnecessary.  And cause hangs on gen8.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:12:01 +00:00
Rob Clark
d3e479b5c5 freedreno/registers: Fix gen8 swizzle enum 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:12:00 +00:00
Rob Clark
39bf9c0222 freedreno/registers: pm4 updates for gen8 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:12:00 +00:00
Rob Clark
fa45a48843 freedreno: Add gen8 chip template-fu 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:12:00 +00:00
Rob Clark
d786b6ad3e freedreno/drm-shim: Add a830 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:59 +00:00
Rob Clark
49c2271f26 freedreno/common: Add placeholder a8xx device 
Enough to have a gpu-id so that cffdump, disasm tests, etc, function.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:59 +00:00
Rob Clark
aa112be635 freedreno/common: Make max tile dimensions a param 
This value may differ between SKUs within a given generation.  So make
them parameters.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:59 +00:00
Rob Clark
96d6755e1f freedreno: Add gen8 device info 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:58 +00:00
Rob Clark
cb4a1134a9 freedreno/event: Extend event helpers for gen8 
There are some new events, but existing ones look the same.  So I think,
at least for now, we can keep the same table for gen7 and gen8.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:58 +00:00
Rob Clark
f35867686d freedreno/lrz: Extend lrz fc helpers for gen8 
The FC RAM is the same size as gen7.  Tbd if the metadata is also the
same.  So far we aren't enabling LRZ on gen8 yet, but need to do
something to make the compiler happy, so treat gen8 as it was the same
as gen7.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:58 +00:00
Rob Clark
ce4373ede5 freedreno/registers: Extend ncrb builder for new gens 
We want to use the A7XX version for anything CHIP>=A7XX.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:58 +00:00
Rob Clark
b5d307ef03 freedreno: Add chip range template helpers 
The c++ syntax for this isn't pretty.  But it is something we need in a
few places, so add some macros to hopefully make things easier on the
eyes.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:58 +00:00
Rob Clark
bcf4c8893c freedreno/registers: Fix GRAS_LRZ_CNTL definition 
Two fields moved to GRAS_LRZ_CNTL2 on a7xx+.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:57 +00:00
Rob Clark
f47c3d554b freedreno/registers: Name HYSTERESIS regs 
It looks like we'll need to program them for gen8.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:57 +00:00
Rob Clark
843ec5dbe7 freedreno/registers: Name RB_LRZ_CNTL2 
We'll need this for LRZ flush sequence on gen8

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:56 +00:00
Rob Clark
5c1bcaca24 freedreno/registers: Rename SP_HLSQ_MODE_CNTL 
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:55 +00:00
Rob Clark
30a0ac7c0f freedreno/registers: Fix a few field names 
Give proper names to a few bitfields that we were already using.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:54 +00:00
Rob Clark
ccdd5eb49d freedreno/decode: Add extra indent levels 
Now we start hitting an extra indent level.

Fixes: d7db333b0e ("freedreno/decode: Add gen8 support")
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:53 +00:00
Rob Clark
e7a01c9c23 freedreno/decode: Print mode for compute shaders 
Similar to draw packets, it is useful to be able to see the mode and
pipe.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
 2025-12-08 22:11:53 +00:00