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ir3: Fix gen8 ldc encoding

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Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
This commit is contained in:
Rob Clark 2025-10-30 14:39:35 -07:00 • committed by Marge Bot
parent e53c605adf
commit 937625c391
2 changed files with 33 additions and 2 deletions
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1
src/freedreno/ir3/tests/disasm.c
View file

@ -425,6 +425,7 @@ static const struct test {
INSTR_6XX(c0260000_00478200, "ldc.offset1.1.imm r0.x, r0.x, 0"), /* ldc.1.mode0.base0 r0.x, r0.x, 0 */
INSTR_6XX(c0260000_00478400, "ldc.offset2.1.imm r0.x, r0.x, 0"), /* ldc.1.mode0.base0 r0.x, r0.x, 0 */
INSTR_6XX(c0260000_00478600, "ldc.offset3.1.imm r0.x, r0.x, 0"), /* ldc.1.mode0.base0 r0.x, r0.x, 0 */
INSTR_8XX(c0260000_00678600, "ldc.offset3.1.imm r0.x, r0.x, 0"),
/* dEQP-VK.glsl.arrays.length.float_fragment */
INSTR_6XX(c02600c1_00c7a900, "ldc.u.offset0.3.imm.base0 r48.y, 0, 0"), /* ldc.u.3.mode4.base0 sr48.y, 0, 0 */

34
src/freedreno/isa/ir3-cat6.xml
View file

@ -1116,19 +1116,26 @@ SOFTWARE.
<bitset name="#cat6-ldc-common" extends="#instruction-cat6-a6xx">
<pattern pos="0" >x</pattern>
<pattern low="14" high="19">011110</pattern> <!-- OPC -->
<pattern low="20" high="22">1xx</pattern>
<pattern pos="20">x</pattern>
<field pos="21" name="SP" type="bool"/>
<derived name="SH" type="bool" display="h">
<expr>!{SP} &amp;&amp; (ISA_GPU_ID() &gt;= 800)</expr>
</derived>
<pattern pos="22">1</pattern>
<field pos="23" name="SRC1_IM" type="bool"/>
<derived name="SRC2_IM" expr="#cat6-direct" type="bool"/>
<field low="41" high="48" name="SRC2" type="#cat6-src">
<param name="SRC2_IM" as="SRC_IM"/>
</field>
<field low="24" high="31" name="SRC1" type="#cat6-src">
<field low="24" high="31" name="SRC1" type="#cat6-src-sp">
<param name="SRC1_IM" as="SRC_IM"/>
<param name="SH"/>
</field>
<pattern low="49" high="51">x11</pattern> <!-- TYPE -->
<encode>
<map name="SRC1_IM">!!(src->srcs[1]->flags &amp; IR3_REG_IMMED)</map>
<map name="SRC1">src->srcs[1]</map>
<map name="SP">ISA_GPU_ID() &gt;= 800</map>
<map name="SRC2">src->srcs[0]</map>
</encode>
</bitset>
@ -1552,6 +1559,29 @@ SOFTWARE.
</encode>
</bitset>
<bitset name="#cat6-src-sp" size="8">
<doc>
Source value that can be either immed or gpr
</doc>
<override>
<expr>{SRC_IM}</expr>
<display>
{IMMED}
</display>
<field name="IMMED" low="0" high="7" type="uint"/>
</override>
<display>
{SH}r{GPR}.{SWIZ}
</display>
<field name="SWIZ" low="0" high="1" type="#swiz"/>
<field name="GPR" low="2" high="7" type="uint"/>
<encode type="struct ir3_register *">
<map name="GPR">src->num >> 2</map>
<map name="SWIZ">src->num &amp; 0x3</map>
<map name="IMMED">extract_reg_iim(src)</map>
</encode>
</bitset>
<bitset name="#cat6-src-const-or-gpr" size="8">
<doc>
Source value that can be either const reg or gpr