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ir3: Add cat3 flut src encoding
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
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c35b5f9726
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4bc01d11b0
5 changed files with 72 additions and 12 deletions
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@ -1738,6 +1738,41 @@ unsigned ir3_cat2_absneg(opc_t opc);
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unsigned ir3_cat3_absneg(struct ir3_compiler *compiler, opc_t opc,
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unsigned src_n);
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static inline bool
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ir3_cat3_int(opc_t opc)
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{
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switch (opc) {
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case OPC_MAD_F16:
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case OPC_MAD_F32:
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case OPC_SEL_F16:
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case OPC_SEL_F32:
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return false;
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case OPC_MAD_U16:
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case OPC_MADSH_U16:
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case OPC_MAD_S16:
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case OPC_MADSH_M16:
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case OPC_MAD_U24:
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case OPC_MAD_S24:
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case OPC_SEL_B16:
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case OPC_SEL_B32:
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case OPC_SEL_S16:
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case OPC_SEL_S32:
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case OPC_SAD_S16:
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case OPC_SAD_S32:
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case OPC_SHRM:
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case OPC_SHLM:
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case OPC_SHRG:
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case OPC_SHLG:
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case OPC_ANDG:
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case OPC_DP2ACC:
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case OPC_DP4ACC:
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case OPC_WMM:
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case OPC_WMM_ACCU:
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default:
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return true;
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}
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}
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/* Return the type (float, int, or uint) the op uses when converting from the
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* internal result of the op (which is assumed to be the same size as the
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* sources) to the destination when they are not the same size. If F32 it does
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@ -839,7 +839,11 @@ cat3_wmm: T_OP_WMM { new_instr(OPC_WMM); }
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cat3_dp: T_OP_DP2ACC { new_instr(OPC_DP2ACC); }
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| T_OP_DP4ACC { new_instr(OPC_DP4ACC); }
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cat3_instr: cat3_opc dst_reg ',' src_reg_or_const_or_rel ',' src_reg_or_const ',' src_reg_or_const_or_rel
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src_reg_or_const_or_rel_or_flut: src_reg_or_const_or_rel
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| flut_immed { new_src(0, IR3_REG_IMMED)->uim_val = $1; }
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| 'h' flut_immed { new_src(0, IR3_REG_IMMED | IR3_REG_HALF)->uim_val = $2; }
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cat3_instr: cat3_opc dst_reg ',' src_reg_or_const_or_rel_or_flut ',' src_reg_or_const ',' src_reg_or_const_or_rel_or_flut
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| cat3_reg_or_const_or_rel_opc dst_reg ',' src_reg_or_const_or_rel_or_imm ',' src_reg_or_const ',' src_reg_or_const_or_rel_or_imm
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| cat3_imm_reg_opc dst_reg ',' src_reg_or_rel_or_imm ',' src_reg_or_const ',' src_reg_or_rel_or_imm
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| cat3_wmm dst_reg ',' src_reg_gpr ',' src_reg ',' immediate
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@ -154,6 +154,7 @@ static const struct test {
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INSTR_7XX(64838806_04088406, "(nop3) sel.b32 r1.z, (last)r1.z, r1.w, (last)r2.x"),
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INSTR_8XX(6206000a_040a0610, "mad.u24 r2.z, 16, r3.x, (last)r2.z"),
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INSTR_8XX(62000800_06030402, "(nop1) mad.u24 r0.x, (last)r0.z, r0.x, 3"),
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INSTR_8XX(63820009_07024409, "mad.f32 r2.y, (neg)(last)r2.y, r1.x, (1.0)"),
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/* cat4 */
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INSTR_6XX(8010000a_00000003, "rcp r2.z, r0.w"),
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@ -271,6 +271,7 @@ __multisrc_case(struct encode_state *s, const struct ir3_register *reg)
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typedef enum {
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REG_CAT3_SRC_GPR,
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REG_CAT3_SRC_ALT_IMMED,
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REG_CAT3_SRC_FLUT,
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REG_CAT3_SRC_CONST_OR_IMMED,
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REG_CAT3_SRC_RELATIVE_GPR,
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REG_CAT3_SRC_RELATIVE_CONST,
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@ -286,18 +287,23 @@ __cat3_src_case(struct encode_state *s, const struct ir3_register *reg)
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return REG_CAT3_SRC_RELATIVE_GPR;
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}
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} else if (reg->flags & IR3_REG_IMMED) {
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switch (s->instr->opc) {
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case OPC_SHRM:
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case OPC_SHLM:
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case OPC_SHRG:
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case OPC_SHLG:
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case OPC_ANDG:
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case OPC_WMM:
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case OPC_WMM_ACCU:
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return REG_CAT3_SRC_CONST_OR_IMMED;
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default:
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if (ir3_cat3_int(s->instr->opc)) {
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switch (s->instr->opc) {
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case OPC_SHRM:
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case OPC_SHLM:
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case OPC_SHRG:
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case OPC_SHLG:
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case OPC_ANDG:
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case OPC_WMM:
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case OPC_WMM_ACCU:
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return REG_CAT3_SRC_CONST_OR_IMMED;
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default:
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assert(s->gen >= 800);
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return REG_CAT3_SRC_ALT_IMMED;
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}
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} else {
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assert(s->gen >= 800);
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return REG_CAT3_SRC_ALT_IMMED;
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return REG_CAT3_SRC_FLUT;
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}
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} else if (reg->flags & IR3_REG_CONST) {
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return REG_CAT3_SRC_CONST_OR_IMMED;
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@ -52,6 +52,20 @@ SOFTWARE.
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</encode>
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</bitset>
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<bitset name="#cat3-src-flut" extends="#cat3-src">
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<gen min="800"/>
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<display>
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{HALF}{IMMED}
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</display>
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<pattern low="8" high="12">00111</pattern>
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<field name="HALF" pos="7" type="bool" display="h"/>
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<assert low="4" high="6">000</assert>
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<field name="IMMED" low="0" high="3" type="#flut"/>
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<encode>
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<map name="IMMED">extract_reg_uim(src)</map>
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<map name="HALF">!!(src->flags & IR3_REG_HALF)</map>
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</encode>
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</bitset>
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<!-- Alternate immed encoding for the !${IMMED_ENCODING} instructions -->
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<bitset name="#cat3-src-alt-immed" extends="#cat3-src">
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