Commit graph

56828 commits

Author SHA1 Message Date
Anuj Phogat
8829b3c37a mesa: Add a helper function _mesa_is_enum_format_unsized()
Function is utilized by next patch in the series.

V2: Add missing formats.

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
(cherry picked from commit e0fe00eeac)
2014-08-06 14:37:04 -07:00
Anuj Phogat
4c02b3d90e mesa: Don't allow snorm internal formats in glCopyTexImage*() in GLES3
Fixes few failures in gles3 Khronos CTS test: packed_pixels

Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
(cherry picked from commit 2d362a6aee)
2014-08-06 14:36:46 -07:00
Anuj Phogat
b6fe3e7ac2 mesa: Add utility function _mesa_is_enum_format_snorm()
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
(cherry picked from commit 845b5ec89f)
2014-08-06 14:36:31 -07:00
Anuj Phogat
323f0246ef mesa: Fix condition for using compressed internalformat in glCompressedTexImage3D()
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
(cherry picked from commit 3c7a0c690a)
2014-08-06 14:36:06 -07:00
Anuj Phogat
686247ff62 mesa: Add error condition for using compressed internalformat in glTexStorage3D()
Fixes gles3 Khronos CTS test: texture_storage_texture_internal_formats

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
(cherry picked from commit e27c9f3a02)
2014-08-06 14:35:46 -07:00
Anuj Phogat
d21e0d34fc mesa: Turn target_can_be_compressed() in to a utility function
V2:  Declare the function in teximage.h

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
(cherry picked from commit ac2adf66c1)
2014-08-06 14:35:17 -07:00
Anuj Phogat
8bb6628cb9 mesa: Fix error condition for valid texture targets in glTexStorage* functions
Fixes gles3 Khronos CTS test: texture_storage_texture_targets

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
(cherry picked from commit a94d78438d)
2014-08-06 14:34:57 -07:00
Ilia Mirkin
69d6ceda43 mesa/st: only convert AND(a, NOT(b)) into MAD when not using native integers
Native integers imply a somewhat different handling of booleans. Instead
of being 1.0/0.0 floats, they are 0 (true) / -1 (false) integers. As such
the original optimization no longer applies.

Reported-by: Glenn Kennard <glenn.kennard@gmail.com>
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 7b3d0a9a1e)
2014-08-06 14:33:51 -07:00
Jordan Justen
1abd1d0430 i965/miptree: Layout 1D Array as 2D Array with height of 1
1D array miptrees were being laid out as a 2D texture with 1 slice.
This happened due to the mesa core storing the 1D array slice count in
the height field. On Intel hardware, we want to create a 2D array with
a height of 1 for the 1D array case.

Fixes assertion failure in piglit (gen6, gen8):
spec/glsl-1.30/execution/tex-miplevel-selection textureOffset 1DArrayShadow

In release builds of Mesa, this test was observed to cause a GPU hang
on gen8.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=81450
Tested-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
(cherry picked from commit c860a379d2)
2014-08-06 14:33:03 -07:00
Roland Scheidegger
3baf37f076 gallivm: fix up out-of-bounds level when using conformant out-of-bound behavior
When using (d3d10) conformant out-of-bound behavior for texel fetching
(currently always enabled) the level still needs to be set to a safe value
even though the offset in the end won't get used because the level is used
to look up the mip offset itself and the actual strides, which might otherwise
crash.
For simplicity, we'll use level 0 in this case (this ought to be safe, llvmpipe
does not actually fill in level 0 information if first_level is larger, but
some random strides / offsets shouldn't hurt as ultimately we always use
offset 0 in this case).
Fixes a crash in some in-house test where random huge levels appear in
lp_build_fetch_texel() (the test actually uses level 0 always but if the
fetching happens in a block with a execution mask random values may appear).

CC: <mesa-stable@lists.freedesktop.org>

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
(cherry picked from commit 5a12155503)
2014-08-06 14:31:48 -07:00
Marek Olšák
853cd6a4f7 radeonsi: use DRAW_PREAMBLE on CIK
It's the same as setting the 3 regs separately, but shorter, and it also
seems to be required on GFX7.2 and later. This doesn't fix Hawaii.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
(cherry picked from commit 315f3c171d)
2014-07-31 15:23:14 -07:00
Christian König
c66da3d457 radeonsi: fix order of r600_need_dma_space and r600_context_bo_reloc
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit c8011c1885)
2014-07-31 15:22:49 -07:00
Marek Olšák
f75dfcee10 radeonsi: fix build because of lack of draw_indirect infrastructure in 10.2 2014-07-31 15:22:21 -07:00
Jason Ekstrand
b9c5a8f869 main/get_hash_params: Add GL_SAMPLE_SHADING_ARB
GL_SAMPLE_SHADING is specified as a valid pname for glGet in the
GL_ARB_sample_shading extension.  It seems as if we forgot to add it to the
table of pnames.

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 3ea922dd7c)
2014-07-30 22:09:46 -07:00
José Fonseca
c84b367b18 st/wgl: Clamp wglChoosePixelFormatARB's output nNumFormats to nMaxFormats.
While running https://github.com/nvMcJohn/apitest with apitrace I noticed that Mesa was producing bogus results:

  wglChoosePixelFormatARB(hdc, piAttribIList = {...}, pfAttribFList = &0, nMaxFormats = 1, piFormats = {19, 65576, 37, 198656, 131075, 0, 402653184, 0, 0, 0, 0, -573575710}, nNumFormats = &12) = TRUE

However https://www.opengl.org/registry/specs/ARB/wgl_pixel_format.txt states

    <nNumFormats> returns the number of matching formats. The returned
    value is guaranteed to be no larger than <nMaxFormats>.

Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
(cherry picked from commit 66a1b3a1da)
2014-07-30 22:09:46 -07:00
Marek Olšák
71102219ea r600g,radeonsi: switch all occurences of array_size to util_max_layer
This fixes 3D texture support in all these cases, because array_size is 1
with 3D textures and depth0 actually contains the "array size".
util_max_layer is universal and returns the last layer index for any texture
target.

A lot of the cases below can't actually be hit with 3D textures, but let's
be consistent.

This fixes a failure in:
    piglit layered-rendering/clear-color-all-types 3d single_level
for r600g and radeonsi, which was caused by an incorrect CMASK size
calculation.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
(cherry picked from commit a9528cef6b)
2014-07-30 22:09:45 -07:00
Marek Olšák
d26ac40bad radeonsi: fix occlusion queries on Hawaii
This was just a guess - and it worked!

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit 71ce92200e)
2014-07-30 22:09:45 -07:00
Marek Olšák
50dcc2eb26 winsys/radeon: fix vram_size overflow with Hawaii
This fixes piglit spec/!OpenGL 3.1/minmax.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit 156b7e244c)
2014-07-30 22:09:45 -07:00
Marek Olšák
0dfcf50639 radeonsi: fix a hang with streamout on Hawaii
I actually couldn't reproduce this one, but internal docs recommend this
workaround. Better safe than sorry.

Also, the number of dwords for the sync packets is increased by 4 instead
of 2, because it wasn't bumped last time when a new packet was added there.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit 0e7f56313d)
2014-07-30 22:09:45 -07:00
Marek Olšák
6ff3da2509 radeonsi: fix a hang with instancing on Hawaii
This fixes "piglit/bin/arb_transform_feedback2-draw-auto instanced".

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit 3d9e87406c)
2014-07-30 22:09:45 -07:00
Marek Olšák
378def4cab gallium/util: add a helper for calculating primitive count from vertex count
This is needed by the following commit which is a candidate for stable too.

Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit c7407b94a8)
2014-07-30 22:09:45 -07:00
Marek Olšák
fcb6c0d2b8 radeonsi: fix CMASK and HTILE calculations for Hawaii
This fixes the checkerboard pattern in glxgears and anything that triggers
fast color clear.

num_channels is always <= 8, but Hawaii has 16 pipes.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit 9b046474c9)
2014-07-30 22:09:45 -07:00
Marek Olšák
d59406cdb7 r600g: switch SNORM conversion to DX and GLES behavior
it also matches GL 4.2

further discussion:
http://lists.freedesktop.org/archives/mesa-dev/2013-August/042680.html

Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit d5bcb5e8de)
2014-07-30 22:09:45 -07:00
Ilia Mirkin
f2023b8dc8 nvc0: make sure that the local memory allocation is aligned to 0x10
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 47e5a8d7a2)
2014-07-30 22:09:45 -07:00
Kenneth Graunke
37114cc2eb i965/fs: Set LastRT on the final FB write on Broadwell.
In Piglit's EXT_framebuffer_multisample/alpha-to-coverage-dual-src-blend
test, key->nr_color_regions == 2, but the dual source blend FB write has
ir->target set to 0.  So we failed to set "Last Render Target Select" on
any FB write message.

We only emit one FB write per render target, so my comment about setting
LastRT on every FB write directed at the last color region is a bit...
misinformed.  According to the documentation, depth buffer writes and
scoreboard updates happen on the FB write with LastRT set, so I believe
we want to set it only once.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit d4d886a0bc)

Conflicts:
	src/mesa/drivers/dri/i965/gen8_fs_generator.cpp
2014-07-30 22:09:45 -07:00
Anuj Phogat
f876eae80b mesa: Don't use memcpy() in _mesa_texstore() for float depth texture data
because float depth texture data needs clamping to [0.0, 1.0]. Let the
_mesa_texstore() fallback to slower path.

Fixes Khronos GLES3 CTS tests:
shadow_execution_vert
shadow_execution_frag

V2: Move the check to _mesa_texstore_can_use_memcpy() function.
    Add check for floating point data types.

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit 9548ba6e7b)
2014-07-30 22:09:45 -07:00
Kenneth Graunke
8e91b094c8 i965/fs: Fix gl_SampleMask handling for SIMD16 on Gen8+.
We actually want to use mov(16), not mov(8).

Fixes 7 Piglit tests: ARB_sample_shading/builtin-gl-sample-mask [2468]
and ARB_sample_shading/builtin-gl-sample-mask-simple [468].

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80991
Reviewed-by: Matt Turner <mattst88@gmail.com>
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 29af97f280)
2014-07-30 22:09:45 -07:00
Kenneth Graunke
6893c25c7b i965/fs: Fix gl_SampleID for 2x MSAA and SIMD16 mode.
We might be able to do this without an extra program key field, but this
is non-invasive and fixes the bug, for now.

This fixes the following Piglit tests on Broadwell:
- ARB_sample_shading/builtin-gl-sample-id 2
- ARB_sample_shading/builtin-gl-sample-position 2
- EXT_framebuffer_multisample/multisample-blit 2 color
- EXT_framebuffer_multisample/multisample-blit 2 color linear
- EXT_framebuffer_multisample/multisample-blit 2 depth
- EXT_framebuffer_multisample/no-color 2 depth combined
- EXT_framebuffer_multisample/no-color 2 depth separate
- EXT_framebuffer_multisample/no-color 2 depth single
- EXT_framebuffer_multisample/no-color 2 depth-computed combined
- EXT_framebuffer_multisample/no-color 2 depth-computed separate
- EXT_framebuffer_multisample/no-color 2 depth-computed single
- EXT_framebuffer_multisample/unaligned-blit 2 color msaa
- EXT_framebuffer_multisample/unaligned-blit 2 depth msaa

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80991
Reviewed-by: Matt Turner <mattst88@gmail.com>
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 38ffef7840)
2014-07-30 22:09:38 -07:00
Kenneth Graunke
62ebb85cd4 i965: Add missing persample_shading field to brw_wm_debug_recompile.
Otherwise, the performance warning for shader recompiles will just say
"something else".

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
(cherry picked from commit 4cf47c80fc)
2014-07-30 16:31:39 -07:00
Jason Ekstrand
8c8dc8c9e9 main/format_pack: Fix a wrong datatype in pack_ubyte_R8G8_UNORM
Before it was only storing one of the color components due to truncation.
With this patch it now properly stores all of them.

Reviewed-by: Brian Paul <brianp@vmware.com>
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit ecd3e89b32)
2014-07-30 16:28:54 -07:00
Anuj Phogat
775895110c i965: Fix z_offset computation in intel_miptree_unmap_depthstencil()
The bug is triggered by using glTexSubImage2d() with GL_DEPTH_STENCIL
as base internal format and non-zero x, y offsets. Currently x, y
offsets are ignored while updating the texture image.

Fixes Khronos GLES3 CTS tests:
npot_tex_sub_image_2d
npot_tex_sub_image_3d
npot_pbo_tex_sub_image_2d
npot_pbo_tex_sub_image_2d

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
(cherry picked from commit 984a02ba55)
2014-07-30 16:28:30 -07:00
Adel Gadllah
386648c555 i915: Fix up intelInitScreen2 for DRI3
Commit 442442026e updated both i915 and i965 for DRI3 support,
but one check in intelInitScreen2 was missed for i915 causing crashes
when trying to use i915 with DRI3.

So fix that up.

Reported-by: Igor Gnatenko <i.gnatenko.brain@gmail.com>
References: https://bugzilla.redhat.com/show_bug.cgi?id=1115323
References: https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=754297
Tested-by: František Zatloukal <Zatloukal.Frantisek@gmail.com>
Tested-by: Dirk Griesbach <spamthis@freenet.de>
Signed-off-by: Adel Gadllah <adel.gadllah@gmail.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit b656e3c603)
2014-07-30 16:27:59 -07:00
Thorsten Glaser
0e6d8ca573 nv50: fix build failure on m68k due to invalid struct alignment assumptions
Make alignment assumptions explicit by inserting correct padding with
unknown struct members.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 3cfe6bc9cc)
2014-07-30 16:27:23 -07:00
Tom Stellard
1233cdd98d clover: Call end_query before getting timestamp result v2
v2:
  - Move the end_query() call into the timestamp constructor.
  - Still pass false as the wait parameter to get_query_result().

Reviewed-by: Niels Ole Salscheider <niels_ole@salscheider-online.de>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

CC: "10.2" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 74dfd86ed6)

Conflicts:
	src/gallium/state_trackers/clover/core/timestamp.cpp
2014-07-30 16:26:44 -07:00
Ian Romanick
7a856002d3 mesa: Don't allow GL_TEXTURE_{LUMINANCE,INTENSITY}_* queries outside compat profile
There are no queries for GL_TEXTURE_LUMINANCE_SIZE,
GL_TEXTURE_INTENSITY_SIZE, GL_TEXTURE_LUMINANCE_TYPE, or
GL_TEXTURE_INTENSITY_TYPE in any version of OpenGL ES or desktop OpenGL
core profile.

NOTE: Without changes to piglit, this regresses
required-sized-texture-formats.

v2: Rebase on different initial change.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Cc: "10.2 <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 9a723b970e)
2014-07-30 16:10:38 -07:00
Ian Romanick
d8074a6a1c mesa: Don't allow GL_TEXTURE_BORDER queries outside compat profile
There are no texture borders in any version of OpenGL ES or desktop
OpenGL core profile.

Fixes piglit's gl-3.2-texture-border-deprecated.

v2: Rebase on different initial change.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Cc: "10.2 <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 750286600b)
2014-07-30 16:10:11 -07:00
Kenneth Graunke
6388ad51ff i965: Enable compressed multisample support (CMS) on Broadwell.
Everything is in place and appears to be working.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
(cherry picked from commit 8cf289c3ef)
2014-07-17 15:59:01 -07:00
Kenneth Graunke
ab0ad8f7e9 i965: Add 2x MSAA support to the MCS allocation function.
2x MSAA also uses 8 bits, just like 4x.  More bits are unused.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
(cherry picked from commit db184d43b0)
2014-07-17 15:59:01 -07:00
Kenneth Graunke
1c386d5c35 i965: Hook up the MCS buffers in SURFACE_STATE on Broadwell.
MCS buffers are never allocated on Broadwell, so this does nothing for
now, but puts the infrastructure in place for when they do exist.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
(cherry picked from commit a248b2a4eb)
2014-07-17 15:59:01 -07:00
Kenneth Graunke
e3c0c23873 i965: Drop SINT workaround for CMS layout on Broadwell.
According to the documentation, we don't need this SINT workaround on
Broadwell.  (Or at least, it doesn't mention that we need it.)

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
(cherry picked from commit e10311be9f)
2014-07-17 15:59:01 -07:00
Kenneth Graunke
2a90fbfce4 i965: Add plumbing for Broadwell's auxiliary surface support.
Broadwell generalizes the MCS fields to allow for multiple kinds of
auxiliary surfaces.  This patch adds the plumbing to set those values,
but doesn't yet hook any up.

v2: (by Jordan Justen) Use mt for qpitch; pitch is tiles - 1.
v3: Don't forget to subtract 1 from aux_mt->pitch.
v4: Drop unnecessary aux_mt->offset (caught by Jordan Justen).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
(cherry picked from commit fd77187689)
2014-07-17 15:59:01 -07:00
Jordan Justen
d374cfe0bc i965: Add auxiliary surface field #defines for Broadwell.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
(cherry picked from commit a46cb6a971)
2014-07-17 15:59:01 -07:00
Matt Turner
b56908d7db i965/fs: Set correct number of regs_written for MCS fetches.
regs_written is in units of virtual GRFs.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit dfd117b857)
2014-07-17 15:59:01 -07:00
Eric Anholt
c6a6acb6b4 i965: Generalize the pixel_x/y workaround for all UW types.
This is the only case where a fs_reg in brw_fs_visitor is used during
optimization/code generation, and it meant that optimizations had to be
careful to not move pixel_x/y's register number without updating it.

Additionally, it turns out we had a couple of other UW values that weren't
getting this treatment (like gl_SampleID), so this more general fix is
probably a good idea (though I wasn't able to replicate problems with
either pixel_[xy]'s values or gl_SampleID, even when telling the register
allocator to reuse registers immediately)

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit 66f5c8df06)
2014-07-17 15:59:00 -07:00
Kenneth Graunke
64ff84abae i965/fs: Use WE_all for gl_SampleID header register munging.
This code should execute without regard to the currently executing
channels.  Asking for gl_SampleID inside control flow might break in
strange ways.  It appears to break even at the top of the program in
SIMD16 mode occasionally as well.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 6dc9e4e22a19108057162d9d8f8c7d559545f8de)
2014-07-17 15:59:00 -07:00
Matt Turner
8f4e03c397 i965/fs: Don't use brw_imm_* unnecessarily.
Using brw_imm_* creates a source with file=HW_REG, and the scheduler
inserts barrier dependencies when it sees HW_REG. None of these are
hardware-registers in the sense that they're special and scheduling
shouldn't touch them. A few of the modified cases already have HW_REGs
for other sources, so it won't allow extra flexibility in some cases.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit c938be8ad2)
(This patch was cherry-picked to make the next commit apply cleanly.)
2014-07-17 15:59:00 -07:00
Kenneth Graunke
258f35441a i965/fs: Set force_uncompressed and force_sechalf on samplepos setup.
gen8_fs_generator uses these to decide whether to set the execution size
to 8 or 16, so we incorrectly made both of these MOVs the full width in
SIMD16 shaders.  (It happened to work out on Gen4-7.)

Setting them should also help inform optimization passes what's really
going on, which could help avoid bugs.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
2014-07-17 15:59:00 -07:00
Kenneth Graunke
cb04294b42 i965: Set execution size to 8 for instructions with force_sechalf set.
Both inst->force_uncompressed and inst->force_sechalf mean that the
generated instruction should be uncompressed and have an execution size
of 8.  We don't require the visitor to set both flags - setting
inst->force_sechalf by itself is supposed to be enough.

On Gen4-7, guess_execution_size() demoted instructions to 8-wide based
on the default compression state.  On Gen8+, we instead set a default
execution size, which worked great...except that we forgot to check
inst->force_sechalf when deciding whether to use 8 or 16.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 1c62126612752f6eedb66f705cc3ff1e11beea5d)
2014-07-17 15:59:00 -07:00
Matt Turner
d389a863f2 i965/vec4: Constant propagate into 2-src math instructions on Gen8.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit 7192207de1)
2014-07-17 15:59:00 -07:00
Matt Turner
7fcfdfb17b i965/fs: Constant propagate into 2-src math instructions on Gen8.
total instructions in shared programs: 1878133 -> 1876986 (-0.06%)
instructions in affected programs:     153007 -> 151860 (-0.75%)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit 038eb649b3)
2014-07-17 15:59:00 -07:00