i965/fs: Fix gl_SampleID for 2x MSAA and SIMD16 mode.

We might be able to do this without an extra program key field, but this
is non-invasive and fixes the bug, for now.

This fixes the following Piglit tests on Broadwell:
- ARB_sample_shading/builtin-gl-sample-id 2
- ARB_sample_shading/builtin-gl-sample-position 2
- EXT_framebuffer_multisample/multisample-blit 2 color
- EXT_framebuffer_multisample/multisample-blit 2 color linear
- EXT_framebuffer_multisample/multisample-blit 2 depth
- EXT_framebuffer_multisample/no-color 2 depth combined
- EXT_framebuffer_multisample/no-color 2 depth separate
- EXT_framebuffer_multisample/no-color 2 depth single
- EXT_framebuffer_multisample/no-color 2 depth-computed combined
- EXT_framebuffer_multisample/no-color 2 depth-computed separate
- EXT_framebuffer_multisample/no-color 2 depth-computed single
- EXT_framebuffer_multisample/unaligned-blit 2 color msaa
- EXT_framebuffer_multisample/unaligned-blit 2 depth msaa

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80991
Reviewed-by: Matt Turner <mattst88@gmail.com>
Cc: "10.2" <mesa-stable@lists.freedesktop.org>

src/mesa/drivers/dri/i965/brw_fs.cpp

@@ -1304,6 +1304,11 @@ fs_visitor::emit_sampleid_setup(ir_variable *ir)
        * populating a temporary variable with the sequence (0, 1, 2, 3),
        * and then reading from it using vstride=1, width=4, hstride=0.
        * These computations hold good for 4x multisampling as well.
+       *
+       * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
+       * the first four slots are sample 0 of subspan 0; the next four
+       * are sample 1 of subspan 0; the third group is sample 0 of
+       * subspan 1, and finally sample 1 of subspan 1.
        */
       fs_inst *inst;
       inst = emit(BRW_OPCODE_AND, t1,
@@ -1313,7 +1318,7 @@ fs_visitor::emit_sampleid_setup(ir_variable *ir)
       inst = emit(BRW_OPCODE_SHR, t1, t1, fs_reg(5));
       inst->force_writemask_all = true;
       /* This works for both SIMD8 and SIMD16 */
-      inst = emit(MOV(t2, brw_imm_v(0x3210)));
+      inst = emit(MOV(t2, brw_imm_v(key->persample_2x ? 0x1010 : 0x3210)));
       inst->force_writemask_all = true;
       /* This special instruction takes care of setting vstride=1,
        * width=4, hstride=0 of t2 during an ADD instruction.

src/mesa/drivers/dri/i965/brw_wm.c

@@ -277,6 +277,8 @@ brw_wm_debug_recompile(struct brw_context *brw,
                       old_key->flat_shade, key->flat_shade);
    found |= key_debug(brw, "per-sample shading",
                       old_key->persample_shading, key->persample_shading);
+   found |= key_debug(brw, "per-sample shading and 2x MSAA",
+                      old_key->persample_2x, key->persample_2x);
    found |= key_debug(brw, "number of color buffers",
                       old_key->nr_color_regions, key->nr_color_regions);
    found |= key_debug(brw, "MRT alpha test or alpha-to-coverage",
@@ -522,6 +524,8 @@ static void brw_wm_populate_key( struct brw_context *brw,
    /* Ignore sample qualifier while computing this flag. */
    key->persample_shading =
       _mesa_get_min_invocations_per_fragment(ctx, &fp->program, true) > 1;
+   if (key->persample_shading)
+      key->persample_2x = ctx->DrawBuffer->Visual.samples == 2;
 
    key->compute_pos_offset =
       _mesa_get_min_invocations_per_fragment(ctx, &fp->program, false) > 1 &&

src/mesa/drivers/dri/i965/brw_wm.h

@@ -62,6 +62,7 @@ struct brw_wm_prog_key {
    GLuint stats_wm:1;
    GLuint flat_shade:1;
    GLuint persample_shading:1;
+   GLuint persample_2x:1;
    GLuint nr_color_regions:5;
    GLuint replicate_alpha:1;
    GLuint render_to_fbo:1;