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i965/fs: Don't use brw_imm_* unnecessarily.
Using brw_imm_* creates a source with file=HW_REG, and the scheduler inserts barrier dependencies when it sees HW_REG. None of these are hardware-registers in the sense that they're special and scheduling shouldn't touch them. A few of the modified cases already have HW_REGs for other sources, so it won't allow extra flexibility in some cases. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
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2 changed files with 5 additions and 5 deletions
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@ -1311,8 +1311,8 @@ fs_visitor::emit_sampleid_setup(ir_variable *ir)
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* These computations hold good for 4x multisampling as well.
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*/
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emit(BRW_OPCODE_AND, t1,
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fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D)),
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fs_reg(brw_imm_d(0xc0)));
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fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD)),
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fs_reg(0xc0));
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emit(BRW_OPCODE_SHR, t1, t1, fs_reg(5));
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/* This works for both SIMD8 and SIMD16 */
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emit(MOV(t2, brw_imm_v(0x3210)));
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@ -1523,7 +1523,7 @@ fs_visitor::rescale_texcoord(ir_texture *ir, fs_reg coordinate,
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fs_reg chan = coordinate;
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chan.reg_offset += i;
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inst = emit(BRW_OPCODE_SEL, chan, chan, brw_imm_f(0.0));
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inst = emit(BRW_OPCODE_SEL, chan, chan, fs_reg(0.0f));
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inst->conditional_mod = BRW_CONDITIONAL_G;
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/* Our parameter comes in as 1.0/width or 1.0/height,
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@ -2386,7 +2386,7 @@ fs_visitor::emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
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unsigned mlen = 0;
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/* Initialize the sample mask in the message header. */
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emit(MOV(brw_uvec_mrf(8, mlen, 0), brw_imm_ud(0)))
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emit(MOV(brw_uvec_mrf(8, mlen, 0), fs_reg(0u)))
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->force_writemask_all = true;
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if (fp->UsesKill) {
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@ -2432,7 +2432,7 @@ fs_visitor::emit_untyped_surface_read(unsigned surf_index, fs_reg dst,
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unsigned mlen = 0;
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/* Initialize the sample mask in the message header. */
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emit(MOV(brw_uvec_mrf(8, mlen, 0), brw_imm_ud(0)))
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emit(MOV(brw_uvec_mrf(8, mlen, 0), fs_reg(0u)))
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->force_writemask_all = true;
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if (fp->UsesKill) {
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