Commit graph

17404 commits

Author SHA1 Message Date
Boyuan Zhang
cda75f182a ci/fluster: remove 3 pass cases resulted by gaps_in_frame
These 3 failed tests are passing now by enabling the gaps_in_frame feature.
Therefore, remove all of them.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36056>
(cherry picked from commit 9b158d0512)
2025-07-30 11:31:10 +02:00
Boyuan Zhang
9f5a3f7bf2 radeon/vcn: add gaps_in_frame flag to h264 sps
Implement gaps_in_frame_num_value_allowed_flag in h264 msg buffer.
Replace hardcoded flag values with defines.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: David Rosca <david.rosca@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36056>
(cherry picked from commit a63e5f015e)
2025-07-30 11:31:10 +02:00
David Rosca
612996291e radv/video: Set correct H264/5 decode minCodedExtent
Cc: mesa-stable
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35997>
(cherry picked from commit 50eaa0c19f)
2025-07-16 16:23:12 +02:00
Samuel Pitoiset
56b0874422 radv/sdma: fix unaligned 96-bits copies on GFX9
On SDMA4, when the pitch isn't aligned, the width needs to be scaled
by 3 for 96-bits formats.

On SDMA5+, the pitch is aligned and the driver doesn't need to fallback
to unaligned copies.

CC: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36067>
(cherry picked from commit a51afbaff8)
2025-07-16 16:23:11 +02:00
Samuel Pitoiset
5e21a042c4 radv: fix the maximum variable descriptor count with inline uniform blocks
It must not be larger than maxInlineUniformBlockSize.

Fixes recent VKCTS
dEQP-VK.api.maintenance3_check.support_count_inline_uniform_block*.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36044>
(cherry picked from commit b7f4e344bc)
2025-07-16 16:23:11 +02:00
Samuel Pitoiset
1523bff2ae radv: fix indexing with variable descriptor count
The Vulkan spec says:
    "If bindingCount is zero or if this structure is not included in
     the pNext chain, the VkDescriptorBindingFlags for each descriptor
     set layout binding is considered to be zero. Otherwise, the
     descriptor set layout binding at
     VkDescriptorSetLayoutCreateInfo::pBindings[i] uses the flags in
     pBindingFlags[i]."

Fixes recent VKCTS dEQP-VK.api.maintenance3_check.*.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13503
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36044>
(cherry picked from commit 36879c4f99)
2025-07-16 16:23:11 +02:00
Autumn Ashton
e30e214b1a radv: Fix handling of NULL pColorAttachmentLocations in vkCmdSetRenderingAttachmentLocations
From the Vulkan spec:
`If pColorAttachmentLocations is NULL, it is
equivalent to setting each element to its index
within the array.`

Use similar logic to what we do in
CmdSetRenderingInputAttachmentIndices to handle
this behaviour properly.

Signed-off-by: Autumn Ashton <misyl@froggi.es>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35948>
(cherry picked from commit 1ceded0c83)
2025-07-16 16:23:09 +02:00
Samuel Pitoiset
caf05cba12 ac/surface: select a different swizzle mode for ASTC formats on GFX12
It seems only 4KiB swizzle works fine with ASTC.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34877>
(cherry picked from commit 2af3ef9305)
2025-07-16 16:23:08 +02:00
Samuel Pitoiset
d1581108b8 ac/surface: use align with NPOT for estimating surface size
ac_estimate_size() triggers an assertion because the block size isn't
aligned to a power of two for ASTC formats.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35879>
(cherry picked from commit cb6f2d9409)
2025-07-16 16:23:07 +02:00
Samuel Pitoiset
3888ef933a radv: disable RB+ with E5B9G9R9 to workaround failures on GFX10.3-GFX11.5
This looks like a hw bug on GFX10.3-GFX11.5 because RB+ seems to only
work as expected when all channels (RGBA) are written. With that format,
RGB channels must be all set or unset but setting the A channel is
legal so far.

This will reduce rendering performance with that format but it's the
less intrusive solution for now. This might be revisited in the near
future, also with more VKCTS coverage.

This has been tested and verified on GFX10.3 (NAVI21) and GFX11
(NAVI31) and GFX12 (NAVI48), unfortunately I don't have GFX11.5 but
let's assume it's broken there too.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13371
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35631>
(cherry picked from commit 10ef9c6a80)
2025-07-16 16:23:07 +02:00
Samuel Pitoiset
4dac50e381 radv: stop disabling the alpha optimization with E5B9G9R9 and RB+
This old workaround was added due to test failures with VKCTS but it
turns out the tests were broken. Color writemask for E5B9G9R9 must be
all RGB or none and some tests are testing various RGB channels which
is illegal.

See https://gitlab.khronos.org/Tracker/vk-gl-cts/-/issues/5821.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35631>
(cherry picked from commit 7017b25d6a)
2025-07-16 16:23:07 +02:00
Rhys Perry
05364ea153 aco/ra: fix repeated compact_linear_vgprs() in get_reg()
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: b7738de4f9 ("aco/ra: rework linear VGPR allocation")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13431
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35838>
(cherry picked from commit dce1d4ad4c)
2025-07-16 16:23:07 +02:00
Rhys Perry
27d61a6fd2 aco: update ctx.block when inserting discard block
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13432
Backport-to: 25.1
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35833>
(cherry picked from commit 21c4400278)
2025-07-02 16:19:32 +02:00
Pierre-Eric Pelloux-Prayer
f3f56a8668 ac/virtio: fix alignment of metadata command
Command size must be aligned to 8.

Tested-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Fixes: 22263616ed ("amd: amdgpu-virtio implementation")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34470>
(cherry picked from commit 3210484fe2)
2025-07-02 16:19:32 +02:00
Hans-Kristian Arntzen
11bc07dcf5 radv: Timestamps are not valid on dedicated sparse queue.
Signed-off-by: Hans-Kristian Arntzen <post@arntzen-software.no>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35766>
(cherry picked from commit ac16b8c439)
2025-07-02 16:19:32 +02:00
Samuel Pitoiset
d9b72d2987 radv: gather nir shader info at the end of radv_optimize_nir()
Otherwise, outputs_read/outputs_written might not be up-to-date
(mostly after nir_remove_dead_variables) and remove_point_size() might
reach an assertion later because the output variable isn't found.

It seems better to run nir_shader_gather_info() at the very end of
radv_optimize_nir() which can change a lot of things anyways.

No fossils-db changes.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35707>
(cherry picked from commit 30ccd97cd2)
2025-07-02 16:19:31 +02:00
Yiwei Zhang
8701d0e4da radv: relax the native_handle_t::numFds requirement
For modern gralloc impl, usually there's other fds appended in the
native_handle_t for gralloc buffer metadata sharing. So numFds can be
greater than 1, while the common agreement is still that the format
plane handles being placed at the beginning in the lack of a standard
format plane fd metadata query mapper api.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13163

Cc: mesa-stable
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35038>
(cherry picked from commit 41d241bf6e)
2025-07-02 16:19:30 +02:00
Rhys Perry
be6ede15eb aco/lower_branches: keep blocks with multiple logical successors
It might be the case that both the branch and exec mask write in a
divergent branch block are removed. try_remove_simple_block() might then
try to remove it, but fail because it has multiple logical successors.
Instead, just skip these blocks.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Backport-to: 25.1
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35202>
(cherry picked from commit 5344abbc56)
2025-07-02 16:19:29 +02:00
Karol Herbst
d6eb93ba7a ac/nir: fix unaligned single component load/stores
This fixes two problems:
1. we need to lower the bit_size according to the alignment.
2. num_components could end up being 0, so we need to round up instead.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13102
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34976>
(cherry picked from commit 4f5ce2d5aa)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35575>
2025-06-18 17:55:47 +02:00
Samuel Pitoiset
71cf1fed4f radv: fix 1x user sample locations on GFX10+
Only GFX10+ can support 1x user sample locations, but MSAA_ENABLE
needs to be enabled.

Fixes new VKCTS coverage dEQP-VK.pipeline.*samples_1*.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35492>
(cherry picked from commit 061bc6151a)
2025-06-18 17:55:47 +02:00
Samuel Pitoiset
e232bf4bcd ac/surface: fix aliasing DCC tilings with HiZ info on GFX12
DCC tilings info needs to be set for all surfaces, including
depth/stencil. But because this is a C union, settings those fields
for depth/stencil surfaces might accidentally overwrite HiZ info.

This fixes rendering issues with RADV_DEBUG=nohiz.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35515>
(cherry picked from commit 251b23f6c2)
2025-06-18 17:55:47 +02:00
Rhys Perry
7d9487439d ac/llvm: convert to integer after reductions
These return floating point types for floating point ops.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Backport-to: 25.1
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35489>
(cherry picked from commit 2ff53fd97c)
2025-06-18 17:55:47 +02:00
Rhys Perry
df1cf8119b ac/llvm: fix overloading of intrinsic names
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Backport-to: 25.1
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35489>
(cherry picked from commit 3c2b3fbd03)
2025-06-18 17:55:47 +02:00
Rhys Perry
706095e8c3 ac/nir: create lowered inverse_ballot
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: b49eab68a8 ("ac/nir: use s_sendmsg(HS_TESSFACTOR) to optimize writing tess factors for gfx11")
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35489>
(cherry picked from commit ac2e36b377)
2025-06-18 17:55:46 +02:00
Samuel Pitoiset
1541e3cd7a radv: fix 3-plane formats with descriptor buffers
Found by inspection.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35455>
(cherry picked from commit 7f7ed18929)
2025-06-18 17:55:46 +02:00
Samuel Pitoiset
aaa489a1d0 radv: make sure to zero-initialize image view descriptors
This prevents a regression from the next commit which would write
garbage for combined image+sampler descriptors and that might break
capture&replay.

It seems also more robust to write zeroes than garbage overall.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35455>
(cherry picked from commit 22e06d65d7)
2025-06-18 17:55:46 +02:00
Pierre-Eric Pelloux-Prayer
e5e959b0fd ac/llvm: rework component trimming in visit_tex
The referenced commit was a step in the right direction, but not
complete.

ac_build_image_opcode returns a vec<4> or a struct<vec<4>, int>
so we can simplify visit_tex. We just need to map these 4/5 values
to the expected layout from NIR.
eg: depth + TFE would produces "<d, x, x, x>, t" so it has to be
transformed into <d, t>.

nir_texop_fragment_mask_fetch_amd + sparse doesn't exist, so it's
another opportunity for simplification.

This is required to get KHR-GL46.sparse_texture2_tests.SparseTexture2Lookup_texture_2d_depth_component16
working properly.
The same test fails with ACO so it probably needs a change in the
same area.

Fixes: c0ef2aa7f8 ("DEPENDENCY: ac/llvm: fix sparse code handling")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35206>
(cherry picked from commit 4a84ebfcb1)
2025-06-18 17:55:45 +02:00
Rhys Perry
333cb92f69 ac/nir: run nir_lower_vars_to_ssa after nir_lower_task_shader
nir_lower_task_shader does nir_lower_returns, so we need this if the
launch_mesh_workgroups was in control flow.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13326
Backport-to: 25.1
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35411>
(cherry picked from commit bc2edf14d8)
2025-06-18 17:55:45 +02:00
Samuel Pitoiset
18aaac6153 radv/meta: fix using the wrong pipeline layout for ASTC decoding
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35359>
(cherry picked from commit f3578973d7)
2025-06-18 17:55:45 +02:00
Georg Lehmann
fc89f9e60d aco: do not use v_cvt_pk_u8_f32 for f2u8
The ISA docs don't mention this, but instead of always truncating
like other integer conversions, this opcode actually uses the single
precision rounding mode.

We could continue to use the opcode and set the rounding mode to rtz
in lower_to_hw_instrs, but I think I should just concede that f2u8
isn't worth the effort.

Fixes: 9bb10b58 ("aco: use v_cvt_pk_u8_f32 for f2u8")

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35391>
(cherry picked from commit d95e90ab5f)
2025-06-18 17:55:45 +02:00
Rhys Perry
b03ee0a308 aco/gfx12: fix VALUReadSGPRHazard with carry-out
fossil-db (gfx1201):
Totals from 370 (0.46% of 79653) affected shaders:
Instrs: 3933639 -> 3935914 (+0.06%)
CodeSize: 20743448 -> 20752068 (+0.04%); split: -0.00%, +0.04%
Latency: 26261246 -> 26261921 (+0.00%); split: -0.00%, +0.00%
InvThroughput: 5363675 -> 5363760 (+0.00%); split: -0.00%, +0.00%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 65f95ae74e ("aco/insert_NOPs: implement VALU -> VALU case for VALUReadSGPRHazard on GFX12")
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35387>
(cherry picked from commit a714a19e16)
2025-06-18 17:55:45 +02:00
Natalie Vock
85af264acc radv/rt: Avoid encoding infinities in box node coords
On Navi33, certain box sorting modes combined with infinity/-infinity in
the child AABBs cause image_bvh64_intersect_ray to return garbage node
pointers.

To avoid this, convert infinity to the maximum representable
floating-point value, which will still intersect with any non-inf ray.

Fixes consistent hangs in DOOM: The Dark Ages.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35254>
(cherry picked from commit 6628ac8ad9)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35412>
2025-06-18 17:55:44 +02:00
Georg Lehmann
afbda6b431 radv: don't accidentally expose samplerFilterMinmax through Vulkan 1.2
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35339>
(cherry picked from commit 297fdc6636)
2025-06-18 17:55:44 +02:00
Rhys Perry
aad33936b6 aco: set vmem_types for args_pending_vmem
fossil-db (gfx1201):
Totals from 0 (0.00% of 79653) affected shaders:

fossil-db (navi31):
Totals from 11 (0.01% of 79653) affected shaders:
Instrs: 4543 -> 4554 (+0.24%)
CodeSize: 23256 -> 23300 (+0.19%)

fossil-db (navi21):
Totals from 8 (0.01% of 79653) affected shaders:
Instrs: 2333 -> 2341 (+0.34%)
CodeSize: 12328 -> 12360 (+0.26%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Backport-to: 25.0
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34978>
(cherry picked from commit 62a9b4b976)
2025-06-18 17:55:44 +02:00
Samuel Pitoiset
e3637cdb69 radv,radeonsi: fix emitting UPDATE_DB_SUMMARIZER_TIMEOUT on GFX12
Not all PFP firmwares for GFX12 have this packet.

Fixes: 47f5d25f93 ("radv,radeonsi: emit UPDATE_DB_SUMMARIZER_TIMEOUT on GFX12")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13312
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35370>
(cherry picked from commit babeb975c4)
2025-06-07 15:44:17 +02:00
Georg Lehmann
250f423546 aco: clamp exponent of 16bit ldexp
The hw uses only a 16bit int, but NIR's src is 32bit.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34073>
(cherry picked from commit a6675f35b2)
2025-06-04 15:52:49 +02:00
Natalie Vock
658a1624a8 radv/rt: Report 256 byte alignment for scratch
This mirrors AMDVLK. 128-byte alignment is possible, but DOOM: The Dark
Ages screws up scratch allocation with alignments <256 bytes.

Fixes hangs in DOOM: The Dark Ages.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35152>
(cherry picked from commit dac6f09451)
2025-06-04 15:52:49 +02:00
David Rosca
3b3e051ba5 radv/video: Set correct minCodedExtent for encode
Cc: mesa-stable
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35261>
(cherry picked from commit 25f7996395)
2025-06-04 15:52:49 +02:00
Samuel Pitoiset
8537a314f6 radv,radeonsi: emit UPDATE_DB_SUMMARIZER_TIMEOUT on GFX12
This try to mitigate the HiZ GPU hang by increasing a timeout. Loosely
based on PAL but I can confirm it delays the hang when
BOTTOM_OF_PIPE_TS is used as a workaround.

This must be emitted when the GFX queue is idle.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35212>
(cherry picked from commit 47f5d25f93)
2025-06-04 15:52:49 +02:00
Samuel Pitoiset
e35c5d643b radv: add radv_disable_hiz_his_gfx12 and enable for Mafia Definitive Edition
This is a workaround for random GPU hangs with HiZ/HiS on GFX12
because the correct fix is complex and it will take time to be
implemented properly.

Mafia Definitive Edition is the first known game affected by this.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13222
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35182>
(cherry picked from commit 2ebfa64be7)
2025-06-04 15:52:47 +02:00
Samuel Pitoiset
5ad7ae003f radv: fix capture/replay with sparse images and descriptor buffer
The sparse image VA needs to be returned to the application for replay.

Reported by Baldur.

VKCTS has coverage but it doesn't verify this yet.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35162>
(cherry picked from commit 63758bc093)
2025-06-04 15:52:47 +02:00
David Rosca
840325c2f7 radv/video: Limit 10bit H265 decode support to stoney and newer
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12132
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35105>
(cherry picked from commit 1608bc20b5)
2025-06-04 15:52:44 +02:00
Samuel Pitoiset
f0f5af73d4 radv: fix non-indexed draws with primitive restart enable
On GFX11+, DISABLE_FOR_AUTO_INDEX=1 automatically disables primitive
restart enable for non-indexed draws.

On GFX10-GFX10.3 the hw considers primitive restart enable for
non-indexed draws and the driver must disable it explicitly.

GFX9 and older gens aren't affected but applying the change for them
simplifies the implementation.

To fix that, move emitting primitive restart enable at draw time
because it needs to know if the draw is indexed or not.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13037
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34996>
(cherry picked from commit 4d1fcd75f9)
2025-05-20 20:18:08 +02:00
Samuel Pitoiset
db7d38ccef radv: fix missing texel scale for unaligned linear SDMA copies
texel_scale was 0 which caused GPU hangs for unaligned linear copies.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13195
Fixes: 4b73d7e817 ("radv: fix SDMA copies for linear 96-bits formats")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35047>
(cherry picked from commit c22d86e844)
2025-05-20 20:18:08 +02:00
Georg Lehmann
4fa2dbdf55 aco: assume sram ecc is enabled on Vega20
There are D16 load issues on Vega20 that are expected if sram ecc is enabled.
It's a professional class chip and I found mentions of it supporting ecc,
so assume it's enabled.

Maybe this could be improved by querying ecc info from the kernel, but
I'm not sure which query should be used.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13189
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12393
Cc: mesa-stable

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35045>
(cherry picked from commit 0257644130)
2025-05-20 20:18:08 +02:00
Hans-Kristian Arntzen
912437c1a3 radv: Consider that DGC might need shader reads of predicated data.
Similar to indirect draw barrier, need similar fixups for conditional
rendering access.

Signed-off-by: Hans-Kristian Arntzen <post@arntzen-software.no>
Cc: mesa-stable
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34956>
(cherry picked from commit e674823d55)
2025-05-20 20:18:07 +02:00
Samuel Pitoiset
91898fbe37 radv: fix conditional rendering with DGC and non native 32-bit predicate
When the hardware doesn't natively support 32-bit predication, the
driver has a fallback which allocates a 64-bit predicate to the upload
BO in order to copy the original value.

But when conditional rendering is enabled in the stateCommandBuffer
which is used by preprocess() and the execute() is recorded also in the
stateCommandBuffer. If the preprocess() is recorded in a different
cmdbuf which is submitted before the cmdbuf that contains execute(),
the fallback (ie. alloc + COPY_DATA) will be performed after. This would
cause the predicate value to be always 0.

To fix that, keep track of the user predication VA which is the only
VA that needs to be used by DGC because it reads 32-bit from the shader.

This fixes a very weird corner case with vkd3d-proton.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13143
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34953>
(cherry picked from commit 3ca2f71f3d)
2025-05-20 20:18:07 +02:00
Samuel Pitoiset
0e15ea9546 radv: fix fetching conditional rendering state for DGC preprocess
This state must be fetched from the stateCommandBuffer, not from the
current cmdbuf which executes the preprocess().

Partial fix for https://gitlab.freedesktop.org/mesa/mesa/-/issues/13143

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34953>
(cherry picked from commit e2625fa9ca)
2025-05-20 20:18:07 +02:00
Rhys Perry
799685659d aco/gfx115: consider point sample acceleration
Like 15428e0d786939a5c7629a9978947c8a9112ce96 in LLVM.

fossil-db (gfx1150):
Totals from 909 (1.14% of 79653) affected shaders:
Instrs: 5840489 -> 5840705 (+0.00%); split: -0.00%, +0.00%
CodeSize: 31133460 -> 31134296 (+0.00%); split: -0.00%, +0.00%
Latency: 52982280 -> 53438577 (+0.86%); split: -0.00%, +0.86%
InvThroughput: 10841454 -> 10942682 (+0.93%); split: -0.00%, +0.93%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Backport-to: 25.0
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34935>
(cherry picked from commit 171920ceed)
2025-05-20 20:18:07 +02:00
Samuel Pitoiset
e81572403c radv: remove the optimization for equal immutable samplers
This optimization used to optimize the allocated space for descriptors
when immutable samplers are equal. Though, this was basically broken :

- descriptor copies were broken for combiner image sampler (or sampler)
  with equal immutable samplers because 96 bytes were copied instead of
  64 bytes (cf. the linked ticket). This could be fixed but it's not
  worth it.
- the value returned by vkGetDescriptorLayoutSupport() was broken, it
  should have been 96 with no immutable samplers (or when they aren't
  equal)

This optimization was also not applied for descriptor buffers which is
the default for vkd3d-proton and Zink. DXVK doesn't use db but it
doesn't use immutable samplers, so basically only native vulkan games
would be concerned.

Note that immutable samplers would still be inlined in shaders if no
indirect access which should be 99.9% of the usecase.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11165
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34928>
(cherry picked from commit 69ff204422)
2025-05-20 20:18:06 +02:00