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ac/surface: fix aliasing DCC tilings with HiZ info on GFX12

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DCC tilings info needs to be set for all surfaces, including
depth/stencil. But because this is a C union, settings those fields
for depth/stencil surfaces might accidentally overwrite HiZ info.

This fixes rendering issues with RADV_DEBUG=nohiz.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35515>
This commit is contained in:
Samuel Pitoiset 2025-06-13 15:55:03 +02:00 • committed by Marge Bot
parent b0604d6938
commit 251b23f6c2
4 changed files with 25 additions and 26 deletions
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12
src/amd/common/ac_surface.c
View file

@ -3632,11 +3632,11 @@ void ac_surface_apply_bo_metadata(enum amd_gfx_level gfx_level, struct radeon_su
surf->u.gfx9.swizzle_mode = AMDGPU_TILING_GET(tiling_flags, GFX12_SWIZZLE_MODE);
surf->u.gfx9.color.dcc.max_compressed_block_size =
AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_MAX_COMPRESSED_BLOCK);
surf->u.gfx9.color.dcc_data_format =
surf->u.gfx9.dcc_data_format =
AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_DATA_FORMAT);
surf->u.gfx9.color.dcc_number_type =
surf->u.gfx9.dcc_number_type =
AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_NUMBER_TYPE);
surf->u.gfx9.color.dcc_write_compress_disable =
surf->u.gfx9.dcc_write_compress_disable =
AMDGPU_TILING_GET(tiling_flags, GFX12_DCC_WRITE_COMPRESS_DISABLE);
scanout = AMDGPU_TILING_GET(tiling_flags, GFX12_SCANOUT);
} else if (gfx_level >= GFX9) {
@ -3683,9 +3683,9 @@ void ac_surface_compute_bo_metadata(const struct radeon_info *info, struct radeo
*tiling_flags |= AMDGPU_TILING_SET(GFX12_SWIZZLE_MODE, surf->u.gfx9.swizzle_mode);
*tiling_flags |= AMDGPU_TILING_SET(GFX12_DCC_MAX_COMPRESSED_BLOCK,
surf->u.gfx9.color.dcc.max_compressed_block_size);
*tiling_flags |= AMDGPU_TILING_SET(GFX12_DCC_NUMBER_TYPE, surf->u.gfx9.color.dcc_number_type);
*tiling_flags |= AMDGPU_TILING_SET(GFX12_DCC_DATA_FORMAT, surf->u.gfx9.color.dcc_data_format);
*tiling_flags |= AMDGPU_TILING_SET(GFX12_DCC_WRITE_COMPRESS_DISABLE, surf->u.gfx9.color.dcc_write_compress_disable);
*tiling_flags |= AMDGPU_TILING_SET(GFX12_DCC_NUMBER_TYPE, surf->u.gfx9.dcc_number_type);
*tiling_flags |= AMDGPU_TILING_SET(GFX12_DCC_DATA_FORMAT, surf->u.gfx9.dcc_data_format);
*tiling_flags |= AMDGPU_TILING_SET(GFX12_DCC_WRITE_COMPRESS_DISABLE, surf->u.gfx9.dcc_write_compress_disable);
*tiling_flags |= AMDGPU_TILING_SET(GFX12_SCANOUT, (surf->flags & RADEON_SURF_SCANOUT) != 0);
} else if (info->gfx_level >= GFX9) {
uint64_t dcc_offset = 0;

15
src/amd/common/ac_surface.h
View file

@ -251,6 +251,13 @@ struct gfx9_surf_layout {
/* DCC or HTILE level info */
struct gfx9_surf_meta_level meta_levels[RADEON_SURF_MAX_LEVELS];
/* Gfx12 DCC recompression settings used by kernel memory management.
* The driver sets these, not ac_compute_surface.
*/
uint8_t dcc_number_type; /* CB_COLOR0_INFO.NUMBER_TYPE */
uint8_t dcc_data_format; /* [0:4]:CB_COLOR0_INFO.FORMAT, [5]:MM */
bool dcc_write_compress_disable;
union {
/* Color */
struct {
@ -264,14 +271,6 @@ struct gfx9_surf_layout {
uint8_t dcc_block_width;
uint8_t dcc_block_height;
uint8_t dcc_block_depth;
/* Gfx12 DCC recompression settings used by kernel memory management.
* The driver sets these, not ac_compute_surface.
*/
uint8_t dcc_number_type; /* CB_COLOR0_INFO.NUMBER_TYPE */
uint8_t dcc_data_format; /* [0:4]:CB_COLOR0_INFO.FORMAT, [5]:MM */
bool dcc_write_compress_disable;
/* Displayable DCC. This is always rb_aligned=0 and pipe_aligned=0.
* The 3D engine doesn't support that layout except for chips with 1 RB.
* All other chips must set rb_aligned=1.

18
src/amd/vulkan/radv_image.c
View file

@ -484,9 +484,9 @@ radv_patch_surface_from_metadata(struct radv_device *device, struct radeon_surf
if (pdev->info.gfx_level >= GFX12) {
surface->u.gfx9.swizzle_mode = md->u.gfx12.swizzle_mode;
surface->u.gfx9.color.dcc.max_compressed_block_size = md->u.gfx12.dcc_max_compressed_block;
surface->u.gfx9.color.dcc_data_format = md->u.gfx12.dcc_data_format;
surface->u.gfx9.color.dcc_number_type = md->u.gfx12.dcc_number_type;
surface->u.gfx9.color.dcc_write_compress_disable = md->u.gfx12.dcc_write_compress_disable;
surface->u.gfx9.dcc_data_format = md->u.gfx12.dcc_data_format;
surface->u.gfx9.dcc_number_type = md->u.gfx12.dcc_number_type;
surface->u.gfx9.dcc_write_compress_disable = md->u.gfx12.dcc_write_compress_disable;
} else if (pdev->info.gfx_level >= GFX9) {
if (md->u.gfx9.swizzle_mode > 0)
surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
@ -786,9 +786,9 @@ radv_image_bo_set_metadata(struct radv_device *device, struct radv_image *image,
if (pdev->info.gfx_level >= GFX12) {
md.u.gfx12.swizzle_mode = surface->u.gfx9.swizzle_mode;
md.u.gfx12.dcc_max_compressed_block = surface->u.gfx9.color.dcc.max_compressed_block_size;
md.u.gfx12.dcc_number_type = surface->u.gfx9.color.dcc_number_type;
md.u.gfx12.dcc_data_format = surface->u.gfx9.color.dcc_data_format;
md.u.gfx12.dcc_write_compress_disable = surface->u.gfx9.color.dcc_write_compress_disable;
md.u.gfx12.dcc_number_type = surface->u.gfx9.dcc_number_type;
md.u.gfx12.dcc_data_format = surface->u.gfx9.dcc_data_format;
md.u.gfx12.dcc_write_compress_disable = surface->u.gfx9.dcc_write_compress_disable;
md.u.gfx12.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
} else if (pdev->info.gfx_level >= GFX9) {
const uint64_t dcc_offset = surface->display_dcc_offset ? surface->display_dcc_offset : surface->meta_offset;
@ -1220,9 +1220,9 @@ radv_image_create_layout(struct radv_device *device, struct radv_image_create_in
const enum pipe_format format = radv_format_to_pipe_format(image->vk.format);
/* Set DCC tilings for both color and depth/stencil. */
image->planes[plane].surface.u.gfx9.color.dcc_number_type = ac_get_cb_number_type(format);
image->planes[plane].surface.u.gfx9.color.dcc_data_format = ac_get_cb_format(pdev->info.gfx_level, format);
image->planes[plane].surface.u.gfx9.color.dcc_write_compress_disable = false;
image->planes[plane].surface.u.gfx9.dcc_number_type = ac_get_cb_number_type(format);
image->planes[plane].surface.u.gfx9.dcc_data_format = ac_get_cb_format(pdev->info.gfx_level, format);
image->planes[plane].surface.u.gfx9.dcc_write_compress_disable = false;
}
if (create_info.bo_metadata && !mod_info &&

6
src/gallium/drivers/radeonsi/si_texture.c
View file

@ -231,9 +231,9 @@ static int si_init_surface(struct si_screen *sscreen, struct radeon_surf *surfac
enum pipe_format format = util_format_get_depth_only(ptex->format);
/* These should be set for both color and Z/S. */
surface->u.gfx9.color.dcc_number_type = ac_get_cb_number_type(format);
surface->u.gfx9.color.dcc_data_format = ac_get_cb_format(sscreen->info.gfx_level, format);
surface->u.gfx9.color.dcc_write_compress_disable = false;
surface->u.gfx9.dcc_number_type = ac_get_cb_number_type(format);
surface->u.gfx9.dcc_data_format = ac_get_cb_format(sscreen->info.gfx_level, format);
surface->u.gfx9.dcc_write_compress_disable = false;
}
if (modifier == DRM_FORMAT_MOD_INVALID &&