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radv: fix 1x user sample locations on GFX10+
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Only GFX10+ can support 1x user sample locations, but MSAA_ENABLE
needs to be enabled.

Fixes new VKCTS coverage dEQP-VK.pipeline.*samples_1*.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35492>
This commit is contained in:
Samuel Pitoiset 2025-06-12 15:03:26 +02:00 • committed by Marge Bot
parent 251b23f6c2
commit 061bc6151a
2 changed files with 14 additions and 12 deletions
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23
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -11094,6 +11094,9 @@ radv_emit_msaa_state(struct radv_cmd_buffer *cmd_buffer)
const struct radv_rendering_state *render = &cmd_buffer->state.render;
const struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
const uint32_t sample_mask = d->vk.ms.sample_mask | ((uint32_t)d->vk.ms.sample_mask << 16);
const bool enable_1x_user_sample_locs =
d->vk.ms.sample_locations_enable && d->sample_location.count > 0 && d->sample_location.per_pixel == 1;
const bool msaa_enable = rasterization_samples > 1 || enable_1x_user_sample_locs;
unsigned log_samples = util_logbase2(rasterization_samples);
unsigned pa_sc_conservative_rast = 0;
unsigned db_alpha_to_mask = 0;
@ -11152,7 +11155,7 @@ radv_emit_msaa_state(struct radv_cmd_buffer *cmd_buffer)
}
}
if (rasterization_samples > 1) {
if (msaa_enable) {
unsigned z_samples = MAX2(render->ds_samples, rasterization_samples);
unsigned ps_iter_samples = radv_get_ps_iter_samples(cmd_buffer);
unsigned log_z_samples = util_logbase2(z_samples);
@ -11196,11 +11199,10 @@ radv_emit_msaa_state(struct radv_cmd_buffer *cmd_buffer)
gfx12_opt_set_context_reg2(cmd_buffer, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, RADV_TRACKED_PA_SC_AA_MASK_X0Y0_X1Y0,
sample_mask, sample_mask);
gfx12_opt_set_context_reg(cmd_buffer, R_028BE0_PA_SC_AA_CONFIG, RADV_TRACKED_PA_SC_AA_CONFIG, pa_sc_aa_config);
gfx12_opt_set_context_reg(cmd_buffer, R_028A48_PA_SC_MODE_CNTL_0, RADV_TRACKED_PA_SC_MODE_CNTL_0,
S_028A48_ALTERNATE_RBS_PER_TILE(pdev->info.gfx_level >= GFX9) |
S_028A48_VPORT_SCISSOR_ENABLE(1) |
S_028A48_LINE_STIPPLE_ENABLE(d->vk.rs.line.stipple.enable) |
S_028A48_MSAA_ENABLE(rasterization_samples > 1));
gfx12_opt_set_context_reg(
cmd_buffer, R_028A48_PA_SC_MODE_CNTL_0, RADV_TRACKED_PA_SC_MODE_CNTL_0,
S_028A48_ALTERNATE_RBS_PER_TILE(pdev->info.gfx_level >= GFX9) | S_028A48_VPORT_SCISSOR_ENABLE(1) |
S_028A48_LINE_STIPPLE_ENABLE(d->vk.rs.line.stipple.enable) | S_028A48_MSAA_ENABLE(msaa_enable));
gfx12_opt_set_context_reg(cmd_buffer, R_02807C_DB_ALPHA_TO_MASK, RADV_TRACKED_DB_ALPHA_TO_MASK, db_alpha_to_mask);
gfx12_opt_set_context_reg(cmd_buffer, R_028C5C_PA_SC_SAMPLE_PROPERTIES, RADV_TRACKED_PA_SC_SAMPLE_PROPERTIES,
S_028C5C_MAX_SAMPLE_DIST(max_sample_dist));
@ -11214,11 +11216,10 @@ radv_emit_msaa_state(struct radv_cmd_buffer *cmd_buffer)
radeon_opt_set_context_reg2(cmd_buffer, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, RADV_TRACKED_PA_SC_AA_MASK_X0Y0_X1Y0,
sample_mask, sample_mask);
radeon_opt_set_context_reg(cmd_buffer, R_028BE0_PA_SC_AA_CONFIG, RADV_TRACKED_PA_SC_AA_CONFIG, pa_sc_aa_config);
radeon_opt_set_context_reg(cmd_buffer, R_028A48_PA_SC_MODE_CNTL_0, RADV_TRACKED_PA_SC_MODE_CNTL_0,
S_028A48_ALTERNATE_RBS_PER_TILE(pdev->info.gfx_level >= GFX9) |
S_028A48_VPORT_SCISSOR_ENABLE(1) |
S_028A48_LINE_STIPPLE_ENABLE(d->vk.rs.line.stipple.enable) |
S_028A48_MSAA_ENABLE(rasterization_samples > 1));
radeon_opt_set_context_reg(
cmd_buffer, R_028A48_PA_SC_MODE_CNTL_0, RADV_TRACKED_PA_SC_MODE_CNTL_0,
S_028A48_ALTERNATE_RBS_PER_TILE(pdev->info.gfx_level >= GFX9) | S_028A48_VPORT_SCISSOR_ENABLE(1) |
S_028A48_LINE_STIPPLE_ENABLE(d->vk.rs.line.stipple.enable) | S_028A48_MSAA_ENABLE(msaa_enable));
radeon_opt_set_context_reg(cmd_buffer, R_028B70_DB_ALPHA_TO_MASK, RADV_TRACKED_DB_ALPHA_TO_MASK,
db_alpha_to_mask);
radeon_opt_set_context_reg(cmd_buffer, R_028804_DB_EQAA, RADV_TRACKED_DB_EQAA, db_eqaa);

3
src/amd/vulkan/radv_queue.c
View file

@ -862,7 +862,8 @@ radv_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs)
if (pdev->info.family >= CHIP_POLARIS10) {
unsigned small_prim_filter_cntl = S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
/* Workaround for a hw line bug. */
S_028830_LINE_FILTER_DISABLE(pdev->info.family <= CHIP_POLARIS12);
S_028830_LINE_FILTER_DISABLE(pdev->info.family <= CHIP_POLARIS12) |
S_028830_SC_1XMSAA_COMPATIBLE_DISABLE(pdev->info.gfx_level >= GFX10);
ac_pm4_set_reg(pm4, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL, small_prim_filter_cntl);
}