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aco: do not use v_cvt_pk_u8_f32 for f2u8

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The ISA docs don't mention this, but instead of always truncating
like other integer conversions, this opcode actually uses the single
precision rounding mode.

We could continue to use the opcode and set the rounding mode to rtz
in lower_to_hw_instrs, but I think I should just concede that f2u8
isn't worth the effort.

Fixes: 9bb10b58 ("aco: use v_cvt_pk_u8_f32 for f2u8")

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35391>
This commit is contained in:
Georg Lehmann 2025-06-07 13:13:11 +02:00 • committed by Marge Bot
parent 07c2b90e25
commit d95e90ab5f
1 changed files with 1 additions and 5 deletions
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6
src/amd/compiler/instruction_selection/aco_select_nir_alu.cpp
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@ -2733,11 +2733,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr)
}
}
} else if (instr->src[0].src.ssa->bit_size == 32) {
if (dst.regClass() == v1b && ctx->program->gfx_level >= GFX11)
bld.vop3(aco_opcode::p_v_cvt_pk_u8_f32, Definition(dst),
get_alu_src(ctx, instr->src[0]));
else
emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_u32_f32, dst);
emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_u32_f32, dst);
} else {
emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_u32_f64, dst);
}