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radv,radeonsi: emit UPDATE_DB_SUMMARIZER_TIMEOUT on GFX12

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This try to mitigate the HiZ GPU hang by increasing a timeout. Loosely
based on PAL but I can confirm it delays the hang when
BOTTOM_OF_PIPE_TS is used as a workaround.

This must be emitted when the GFX queue is idle.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35212>
(cherry picked from commit 47f5d25f93)
This commit is contained in:
Samuel Pitoiset 2025-05-29 13:58:33 +02:00 • committed by Eric Engestrom
parent f50f92716f
commit 8537a314f6
4 changed files with 23 additions and 1 deletions
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2
.pick_status.json
View file

@ -1334,7 +1334,7 @@
"description": "radv,radeonsi: emit UPDATE_DB_SUMMARIZER_TIMEOUT on GFX12",
"nominated": true,
"nomination_type": 1,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": null,
"notes": null

3
src/amd/common/sid.h
View file

@ -324,6 +324,9 @@
#define S_D10_CACHE_POLICY(x) ((x & 3) << 2)
#define S_D10_POLL_INTERVAL(x) ((x & 0xFFFF) << 16)
#define PKT3_UPDATE_DB_SUMMARIZER_TIMEOUT 0xEF /* GFX12+ */
#define S_EF1_SUMM_CNTL_EVICT_TIMEOUT(x) ((x & 0xFFF) << 0)
#define PKT2_NOP_PAD PKT_TYPE_S(2)
#define PKT3_NOP_PAD PKT3(PKT3_NOP, 0x3fff, 0) /* header-only version */

8
src/amd/vulkan/radv_queue.c
View file

@ -699,6 +699,14 @@ radv_emit_ge_rings(struct radv_device *device, struct radeon_cmdbuf *cs, struct
S_0309AC_PAF_TEMPORAL(gfx12_store_high_temporal_stay_dirty) |
S_0309AC_PAB_TEMPORAL(gfx12_load_last_use_discard) | S_0309AC_SPEC_DATA_READ(gfx12_spec_read_auto) |
S_0309AC_FORCE_SE_SCOPE(1) | S_0309AC_PAB_NOFILL(1)); /* R_0309AC_GE_PRIM_RING_SIZE */
if (pdev->info.gfx_level == GFX12) {
/* Mitigate the HiZ GPU hang by increasing a timeout when BOTTOM_OF_PIPE_TS is used as the
* workaround. This must be emitted when the gfx queue is idle.
*/
radeon_emit(PKT3(PKT3_UPDATE_DB_SUMMARIZER_TIMEOUT, 0, 0));
radeon_emit(S_EF1_SUMM_CNTL_EVICT_TIMEOUT(0xfff));
}
}
radeon_end();

11
src/gallium/drivers/radeonsi/si_state_shaders.cpp
View file

@ -5160,6 +5160,17 @@ static void si_emit_spi_ge_ring_state(struct si_context *sctx, unsigned index)
S_0309AC_SPEC_DATA_READ(gfx12_spec_read_auto) |
S_0309AC_FORCE_SE_SCOPE(1) |
S_0309AC_PAB_NOFILL(1)); /* R_0309AC_GE_PRIM_RING_SIZE */
if (sctx->gfx_level == GFX12) {
/* Mitigate the HiZ GPU hang by increasing a timeout when
* BOTTOM_OF_PIPE_TS is used as the workaround. This must be
* emitted when the gfx queue is idle.
*/
const uint32_t timeout = sscreen->options.alt_hiz_logic ? 0xfff : 0;
radeon_emit(PKT3(PKT3_UPDATE_DB_SUMMARIZER_TIMEOUT, 0, 0));
radeon_emit(S_EF1_SUMM_CNTL_EVICT_TIMEOUT(timeout));
}
}
radeon_end();
}