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217080 commits

Author SHA1 Message Date
Paulo Zanoni
b52b1a08bf intel/blorp: add blorp_shaders.cl
This gives us the infrastructure that allows us to slowly migrate
pieces of blorp shaders from NIR to OpenCL, which, IMHO, are much
easier to read. We can't fully migrate everything due to all the
conditional building we do with these shaders, but I'm sure we'll find
opportunities to replace some NIR with OpenCL eventually.

The conversion of blorp_check_in_bounds() serves as the first example.

I also plan to have the shaders from the new indirect copy extension
be OpenCL shaders (mixed with some NIR as well), so having this patch
merged now will reduce the diff for the extension later.

Thanks to Alyssa Rosenzweig for her help here.

v2:
- Use SPDX (Alyssa).
- Use nir_trim_vector() (Alyssa).
- Adjust CL variable declaration (Alyssa).

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39046>
2026-01-15 04:34:55 +00:00
Paulo Zanoni
f047f0b1be intel/blorp: unionize blorp_params->wm_inputs
We have two distinct code paths sharing blorp_params->wm_inputs for
different purposes: the code from blorp_blit.c and the code from
blorp_clear.c. While blorp_blit.c uses most of the parameters (all
except clear_color), blorp_clear.c only uses clear_color and
bounds_rect. Split the parameters in two structs: one for blits and
the other for clears.

This not only helps save some space in the shader inputs, but it also
organizes things so it's more clear which parameters are used by what.
In addition, my plan is to later add struct blorp_wm_inputs_indirect,
which won't share anything that the others use, and would otherwise
grow the struct even more.

This change would reduce the size of struct blorp_wm_inputs from 96 to
80, but we have to add padding due to the assertion that compares it
to cs_prog_data->push.cross_thread.size. Still good, though.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39046>
2026-01-15 04:34:55 +00:00
Paulo Zanoni
a8dd4382bf intel/blorp: generate the fast_clear_surf shaders later
Because blorp_params_get_clear_kernel() calls
blorp_params_get_clear_kernel_cs(), which reads params->num_samples,
which we have not properly set yet at this point.

I am also planning to have the functions that create the shader to
rely on params.op, which we have not set yet either.

I found this by inspection (when writing another patch), I'm not sure
if this fixes something relevant, but it may be relevant to ver >= 30
multi-sampled cases.

Fixes: de0c547448 ("blorp: Handle 2D MSAA array image copies on compute shader")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39046>
2026-01-15 04:34:55 +00:00
Paulo Zanoni
e360afdb8a intel/blorp: blorp_blit_vars_init() doesn't need 'key'
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39046>
2026-01-15 04:34:55 +00:00
Paulo Zanoni
39a78f764a blorp: reorganize struct blorp_params
When I first looked at this struct, my tiny little brain felt
overwhelmed.

- Add some white spaces in order to group the parameters into
  "logical" groups so it's easier to reason about everything.

- Change the parameter order just a little bit - without breaking the
  logical groups - so the struct size decreases by 1.7% to 1864 bytes.

- Add a comment explaining what the void * pointers point to.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39046>
2026-01-15 04:34:55 +00:00
Paulo Zanoni
c98f5e9994 blorp: replace magic '2' with BLORP_NUM_BT_ENTRIES
If we ever add more entries, things won't explode.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39046>
2026-01-15 04:34:55 +00:00
Paulo Zanoni
814cfa909d blorp: fix argument indentation
I'm sorry, but I have OCD and the rest of the file is nicely aligned.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39046>
2026-01-15 04:34:55 +00:00
Paulo Zanoni
548d172094 hasvk: restore anv_is_aligned()
On Broadwell, using the debug mode, you can't create even a single
VkImage:

    createimage: ../../src/util/u_math.h:829: util_is_aligned: Assertion `(a != 0) && ((a & (a - 1)) == 0)' failed.

    Thread 1 "createimage" received signal SIGABRT, Aborted.
    Download failed: Invalid argument.  Continuing without source file ./nptl/./nptl/pthread_kill.c.
    __pthread_kill_implementation (threadid=<optimized out>, signo=signo@entry=6, no_tid=no_tid@entry=0) at ./nptl/pthread_kill.c:44
    warning: 44	./nptl/pthread_kill.c: No such file or directory
    (gdb) bt
    #0  __pthread_kill_implementation (threadid=<optimized out>, signo=signo@entry=6, no_tid=no_tid@entry=0) at ./nptl/pthread_kill.c:44
    #1  0x00007ffff789573f in __pthread_kill_internal (threadid=<optimized out>, signo=6) at ./nptl/pthread_kill.c:89
    #2  0x00007ffff7840462 in __GI_raise (sig=sig@entry=6) at ../sysdeps/posix/raise.c:26
    #3  0x00007ffff78284ac in __GI_abort () at ./stdlib/abort.c:77
    #4  0x00007ffff7828420 in __assert_fail_base (fmt=<optimized out>, assertion=<optimized out>, file=<optimized out>, line=829, function=<optimized out>) at ./assert/assert.c:118
    #5  0x00007ffff5a5fb0c in util_is_aligned (n=0, a=0) at ../../src/util/u_math.h:829
    #6  0x00007ffff5a6060d in memory_range_end (memory_range=...) at ../../src/intel/vulkan_hasvk/anv_image.c:51
    #7  0x00007ffff5a61c52 in check_memory_range_s (p=0x7fffffffd800) at ../../src/intel/vulkan_hasvk/anv_image.c:779
    #8  0x00007ffff5a61ef3 in check_memory_bindings (device=0x555555654d50, image=0x55555566e050) at ../../src/intel/vulkan_hasvk/anv_image.c:830
    #9  0x00007ffff5a62ea3 in anv_image_init (device=0x555555654d50, image=0x55555566e050, create_info=0x7fffffffd9d0) at ../../src/intel/vulkan_hasvk/anv_image.c:1263
    #10 0x00007ffff5a63147 in anv_image_init_from_create_info (device=0x555555654d50, image=0x55555566e050, pCreateInfo=0x7fffffffda80) at ../../src/intel/vulkan_hasvk/anv_image.c:1333
    #11 0x00007ffff5a63211 in anv_CreateImage (_device=0x555555654d50, pCreateInfo=0x7fffffffda80, pAllocator=0x0, pImage=0x7fffffffdd20) at ../../src/intel/vulkan_hasvk/anv_image.c:1356
    #12 0x00007ffff44ff376 in vvl::dispatch::Device::CreateImage (this=0x55555562c480, device=0x555555654d50, pCreateInfo=0x7fffffffdcb8, pAllocator=0x0, pImage=0x7fffffffdd20)
        at ./layers/vulkan/generated/dispatch_object.cpp:1160
    #13 0x00007ffff43e8214 in vulkan_layer_chassis::CreateImage (device=0x555555654d50, pCreateInfo=0x7fffffffdcb8, pAllocator=0x0, pImage=0x7fffffffdd20) at ./layers/vulkan/generated/chassis.cpp:2181
    #14 0x0000555555560af4 in vks::Image::init (this=0x7fffffffdcb0) at /home/przanoni/git/random-stuff/vk/vks/libvulkanscript.hpp:1298
    #15 0x000055555556557d in main () at createimage.cpp:36

Since we haven't noticed this issue as quickly as I imagined we would,
let's opt for what's mostly a revert of the behavior change in the
original commit.

Fixes: 7be63ef956 ("intel: do not NIH util_is_aligned")
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39045>
2026-01-15 04:20:29 +00:00
Mike Blumenkrantz
c9e523be97 zink: allow rendering to emulated alpha images for clears
Some checks are pending
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when executing a renderpass which is only a clear, an emulated alpha
image will have the correct value applied from having the clear value
rewritten. this still can't handle draws, but it's a small expansion of
functionality which fixes some edge cases

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39318>
2026-01-15 01:33:20 +00:00
Mike Blumenkrantz
cf9c23a5e2 zink: correctly use GENERAL layout for dynamic texture clears
missed this case

Fixes: 622612f67e ("zink: hook up global GENERAL image layouts")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39318>
2026-01-15 01:33:20 +00:00
Ian Romanick
d19ea686d3 iris/elk: Restore setting nir->num_uniforms to zero.
Elk still uses param array, so it depends on this behavior. This fixes
an assertion failure on Broadwell in gfxbench4/carchase/339.shader_test.

src/intel/compiler/elk/elk_fs_nir.cpp:148: void fs_nir_setup_uniforms(elk_fs_visitor&): Assertion `s.uniforms == s.prog_data->nr_params' failed.

Fixes: f4a0e05970 ("anv/brw/iris: get rid of param array on prog_data")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39280>
2026-01-15 01:13:24 +00:00
Natalie Vock
6f076cdfda radv: Use wave32 for RT on gfx11+
ACO got a lot better at forming VOPD instructions, and testing
feedback seems to point in a slightly positive direction for this.

gfx12 will also start requiring wave32 for dynamic VGPR allocation at
some point.

Measurements on navi31:

Cyberpunk 2077:
Difference at 95.0% confidence
        1.12333 +/- 0.42876
        1.88216% +/- 0.718391%
        (Student's t, pooled s = 0.189165)

Black Myth Wukong benchmark:
Difference at 95.0% confidence
        4 +/- 1.30862
        13.9535% +/- 4.56495%
        (Student's t, pooled s = 0.57735)

Portal with RTX:
66.2ms->61.5ms (~7.64% improvement)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39275>
2026-01-14 23:39:24 +00:00
Aitor Camacho
fcf53988c4 nir/opt_varyings: Support implementations that cannot compact 16-bits
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Add nir_io_compact_to_higher_16 flag so that the pass knows if it can
compact 16-bit varyings into the higher 16 bits of a 32-bit varying.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Aitor Camacho <aitor@lunarg.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38994>
2026-01-14 20:44:41 +00:00
Georg Lehmann
fdfe3acdf0 nir/constant_expression: remove fquantize2f16 denorm special case
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Unnessecary, as any fp32 denorm would be 0 here already.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39266>
2026-01-14 17:05:24 +00:00
Georg Lehmann
631a7ef92a nir: make fquantize2f16 32bit only
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39266>
2026-01-14 17:05:24 +00:00
Alejandro Piñeiro
ec4bcbd26d pan/bi: report stats only if the shaders got compiled
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There are some situations where we don't get a binary. In those cases
it is not relevant to report the statistics.

This was detected while using shader-db, with a shader that has a xfb
vertex shader that was not writing to gl_Position. It that case
IDVS_POSITION binary was zero, so later compiling IDVS_VARYING was
skipped. Due the skip, the pan_stat structure was not initialized, so
the debug used the wrong isa, that used different measurements. This
lead to shader-db report tool failing, due having a mix-up of
measurements.

Although an alternative would be to try to ensure that the structure
is always initialized, seems just more natural to just not report on
shaders with empty binaries (as the stats would be zero for all
measurements).

Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39310>
2026-01-14 15:38:40 +00:00
Natalie Vock
cc81c7de23 nir,aco: Clean up useless lowering of sbt_base_amd
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29580>
2026-01-14 14:19:07 +00:00
Natalie Vock
902c7e9df8 docs: Document RADV/ACO function calls
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29580>
2026-01-14 14:19:07 +00:00
Natalie Vock
27c0326391 radv: Re-enable RT pipelines
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29580>
2026-01-14 14:19:07 +00:00
Natalie Vock
0a1911b220 radv,aco: Use function call structure for RT programs
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29580>
2026-01-14 14:19:07 +00:00
Natalie Vock
c5d796c902 radv/rt: Use function call structure in NIR lowering
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29580>
2026-01-14 14:19:06 +00:00
Natalie Vock
d3cb8b4046 radv: Refactor RT lowering decisions and add RADV_PERFTEST CPS override
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29580>
2026-01-14 14:19:06 +00:00
Natalie Vock
63c019f5be radv: Temporarily disable RT pipelines
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29580>
2026-01-14 14:19:05 +00:00
Natalie Vock
06c2e90e35 aco: Note if a parameter needs to be explicitly preserved
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29580>
2026-01-14 14:19:05 +00:00
Natalie Vock
2bf403ccec aco: Remove bypass_reg_preservation
Not needed anymore

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29580>
2026-01-14 14:19:05 +00:00
Natalie Vock
8525993d02 aco/ra: Move register preservation logic in last block to p_return
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29580>
2026-01-14 14:19:05 +00:00
Natalie Vock
9d2c3c3db2 nir/intrinsics: Add incoming/outgoing payload load/store instructions
With RT function calls, these are going to get lowered to:
- load/store_param (incoming payload)
- load/store_var (outgoing payload)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29580>
2026-01-14 14:19:05 +00:00
Natalie Vock
eb86ae3b8c aco/spill_preserved: Fix spilled VGPR overflow handling
We modified the spill offset inside the function, which made subsequent
calls to emit_vgpr_spills_reloads reload from the wrong offset.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29580>
2026-01-14 14:19:05 +00:00
Natalie Vock
d563415100 radv: Add traversal stack size to cache
We just... didn't do this at all??? I have no idea how this didn't blow
up before, given that plenty of apps should generate a traversal shader
that spills (and thus has a large stack size), but it did finally blow
up in function-call related work.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29580>
2026-01-14 14:19:05 +00:00
Erik Faye-Lund
7e8ef76ef7 panfrost/ci: add warning about g720 results
Some checks are pending
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Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39034>
2026-01-14 13:26:04 +00:00
Erik Faye-Lund
8e12da6c29 panfrost/ci: remove fixed failures
G720 isn't wired up in CI, and nobody is running these regularly. So we
have missed that these CTS issues were fixed upstream.

I haven't actually verified that this works, because I don't have a G720
around at the moment. But the fixes fixed both v10 and v13 GPUs, so it
would be really, really strange if this wasn't effective on v11 as well.

Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39034>
2026-01-14 13:26:04 +00:00
Erik Faye-Lund
136c6ec14e panfrost/ci: remove fixed CTS-flakes
This issue was fixed in the CTS a long time ago, let's remove the
expected flakes.

Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39034>
2026-01-14 13:26:04 +00:00
Rhys Perry
7a09e4a740 aco: use correct addition opcodes in gfx6-8 RT prolog
Some checks are pending
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Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 60dd9d797e ("aco: Swizzle ray launch IDs in the RT prolog")
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39232>
2026-01-14 11:23:42 +00:00
Rhys Perry
da728d5a1a aco: micro-optimize ray launch ID swizzling
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39232>
2026-01-14 11:23:42 +00:00
Lionel Landwerlin
fd744b0c8a brw: switch buffer/image size intrinsics lowering to NIR
Fossil-db DG2:

Totals from 127 (0.01% of 1799288) affected shaders:
Instrs: 60593 -> 60508 (-0.14%); split: -0.15%, +0.01%
Cycle count: 7099635 -> 7116148 (+0.23%); split: -0.12%, +0.35%
Spill count: 468 -> 466 (-0.43%)
Fill count: 224 -> 222 (-0.89%)
Max live registers: 6418 -> 6424 (+0.09%); split: -0.06%, +0.16%
Non SSA regs after NIR: 11228 -> 11220 (-0.07%); split: -0.20%, +0.12%

Fossil-db LNL:

Totals from 135 (0.01% of 1573226) affected shaders:
Instrs: 55173 -> 55143 (-0.05%); split: -0.07%, +0.01%
Cycle count: 9178338 -> 9157052 (-0.23%); split: -0.32%, +0.09%
Spill count: 454 -> 452 (-0.44%)
Fill count: 181 -> 179 (-1.10%)
Max live registers: 12915 -> 12919 (+0.03%); split: -0.06%, +0.09%
Non SSA regs after NIR: 10860 -> 10852 (-0.07%); split: -0.20%, +0.13%

shader-db LNL:

total instructions in shared programs: 16911578 -> 16911566 (<.01%)
instructions in affected programs: 1602 -> 1590 (-0.75%)
helped: 7
HURT: 0
helped stats (abs) min: 1.0 max: 2.0 x̄: 1.71 x̃: 2
helped stats (rel) min: 0.48% max: 1.10% x̄: 0.75% x̃: 0.74%
95% mean confidence interval for instructions value: -2.17 -1.26
95% mean confidence interval for instructions %-change: -0.96% -0.55%
Instructions are helped.

total loops in shared programs: 5168 -> 5168 (0.00%)
loops in affected programs: 0 -> 0
helped: 0
HURT: 0

total cycles in shared programs: 848964184 -> 848955094 (<.01%)
cycles in affected programs: 1528020 -> 1518930 (-0.59%)
helped: 9
HURT: 6
helped stats (abs) min: 2.0 max: 8484.0 x̄: 1212.89 x̃: 20
helped stats (rel) min: 0.02% max: 3.23% x̄: 0.57% x̃: 0.11%
HURT stats (abs)   min: 2.0 max: 1608.0 x̄: 304.33 x̃: 15
HURT stats (rel)   min: <.01% max: 0.59% x̄: 0.19% x̃: 0.07%
95% mean confidence interval for cycles value: -1875.18 663.18
95% mean confidence interval for cycles %-change: -0.75% 0.23%
Inconclusive result (value mean confidence interval includes 0).

total spills in shared programs: 3345 -> 3345 (0.00%)
spills in affected programs: 0 -> 0
helped: 0
HURT: 0

total fills in shared programs: 1777 -> 1777 (0.00%)
fills in affected programs: 0 -> 0
helped: 0
HURT: 0

total sends in shared programs: 869299 -> 869299 (0.00%)
sends in affected programs: 0 -> 0
helped: 0
HURT: 0

LOST:   0
GAINED: 0

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39258>
2026-01-14 10:37:32 +00:00
Erik Faye-Lund
6293137d77 docs: use option-directive
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These arguments misrenders, and gets rendered using a long hyphen
instead of double dashes. Let's fix this by using the Sphinx
option-directive, which is meant for exactly this purpose instead.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39286>
2026-01-14 09:16:24 +00:00
Erik Faye-Lund
0b76d0a70b docs: upgrade bootstrap to 5.3.8
Nothing super important happened that we need here, but it seems like a
good idea to keep up with the latest and greatest anyway...

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39291>
2026-01-14 09:01:17 +00:00
Alyssa Rosenzweig
8e8fa5b20f hk: unify tex builders
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39271>
2026-01-14 08:18:15 +00:00
Alyssa Rosenzweig
8522840541 asahi: use nir_txf
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39271>
2026-01-14 08:18:15 +00:00
Alyssa Rosenzweig
e98728de3c radv: cleanup texture builder
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39271>
2026-01-14 08:18:15 +00:00
Alyssa Rosenzweig
5b44724ad2 vk/meta_copy_fill_update: simplify tex builder
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39271>
2026-01-14 08:18:15 +00:00
Alyssa Rosenzweig
c339b55f92 brw/nir_lower_fs_load_output: unify texture builders
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39271>
2026-01-14 08:18:15 +00:00
Alyssa Rosenzweig
41cdc548ee nir/builder: infer txf_ms/txl/txb opcodes
I'm not convinced these really should be separate opcodes at all in NIR, but
that's not what this patch is about. Here we just infer the opcodes in the
texture builder to allow simplified usage.

This lets us drop nir_txl() & nir_txb() helpers in favour of nir_tex(.lod/bias)
which is more normalized. We could also drop nir_txf_ms in favour of nir_txf but
that affects more callsites and is not obviously a win (unlike nir_txl which is
used once and nir_txb which is unused).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39271>
2026-01-14 08:18:15 +00:00
Samuel Pitoiset
76e7a1cde4 ac/sdma: fix stencil only copies on GFX9
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
macOS-CI / macOS-CI (xlib) (push) Waiting to run
Use the correct pitch per elements for stencil only surfaces.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39281>
2026-01-14 07:39:02 +00:00
Collabora's Gfx CI Team
bb5521e88a Uprev Piglit to 62d499d63d2b8b29a67efd9d93ed9b6a94d4950e
2842979ebe...62d499d63d

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38962>
2026-01-14 06:57:19 +00:00
Sergi Blanch Torne
f55878e49f ci,piglit: update expectations from gc2000 piglit nightly
Expectation changes for the gc2000 piglit job executed on the nightly run, to
separate them from the changes related with the piglit uprev.

Those results comes from stressing 5 times the `gc2000-piglit` jobs in the
nightly run https://gitlab.freedesktop.org/mesa/mesa/-/pipelines/1580535
and use ci-collate.

Signed-off-by: Sergi Blanch Torne <sergi.blanch.torne@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38962>
2026-01-14 06:57:19 +00:00
Ella Stanforth
9f740b26a6 pvr: Fix bugs in the format table
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
macOS-CI / macOS-CI (xlib) (push) Waiting to run
Fixes: 0f0938ed2e ("pvr: Convert format table to indexing with pipe_format")

Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39240>
2026-01-14 00:58:18 +00:00
Rob Clark
39e949434c tu: Move CP_SET_SUBDRAW_SIZE out of SDS
It is not allowed in SDS.  This matters on gen8.

Possibly it wasn't enforced, or worked by luck, on older gens.  But at
least for gen7 and gen8 it is documented as not allowed in SDS (so
working or not may depend on fw version, phase of the moon, etc).

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39254>
2026-01-14 00:06:49 +00:00
Rob Clark
f359b59515 tu: Move PC_DS_PARAM emit after early-exit
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39254>
2026-01-14 00:06:49 +00:00
Rob Clark
0edbafcb37 tu: Track dirty TCS state
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39254>
2026-01-14 00:06:49 +00:00