On Wayland, if the wl_drm interface is not available, for example if the
compositor is using the proprietary NVIDIA driver along with their egl-wayland
library, the device_select layer will fail to initialize. However, the failure
path will unconditionally call wl_drm_destroy even though info.wl_drm would be
NULL in that case. This can cause a segfault in libwayland-client.so.
To fix this, check if info.wl_drm is NULL before calling wl_drm_destroy. This
way, initialization will fail gracefully even if that interface is not present.
Signed-off-by: Erik Kurzinger <ekurzinger@nvidia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10598>
(cherry picked from commit f4eb13dc55)
DXVK 1.8.1 marks position as always invariant but the DX12 version
of the game has the same issue and it's not yet fixed on the
vkd3d-proton side.
Fixes some Z-fighting on GFX10.3.
Cc: 21.1 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11029>
(cherry picked from commit 816be7d46f)
When drawing using util_translate_prim_restart_ib, zink explicitly
ignores pipe_draw_start_count_bias::start, because
util_translate_prim_restart_ib used to create a new index-buffer without
padding at the start.
This makes a lot of sense, because creating a padded index buffer is
just wasteful.
So let's walk back on the choice of starting to pad the output buffer.
Fixes: 1272c2e052 ("util/prim_restart: fix util_translate_prim_restart_ib")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4851
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11059>
(cherry picked from commit 05bb449610)
It is valid to not have a sampler view declaration for the corresponding
sampler in a TGSI shader, and hence we should not rely on the sampler view
declaration to determine if we need to adjust the unnormalized coordinates
for texture rectangle sampling.
This patch is to prep for tgsi shaders that are translated from nir which
in many cases do not issue sampler view declarations.
Fixes: 584b107037 ("st/mesa: Drop the TGSI paths for drawpixels and use nir-to-tgsi")
Reviewed-by: Neha Bhende <bhenden@vmware.com
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11011>
(cherry picked from commit fda4eaf5c4)
Sometimes, TGSI shader doesn't have SVIEW declaration if it is not
utilize in shader. In such cases, declare those resources with the
help of information stored in shader key.
Fixes: 584b107037 ("st/mesa: Drop the TGSI paths for drawpixels and use nir-to-tgsi")
Tested with piglit, gleretrace
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11011>
(cherry picked from commit fd98649091)
When we emit constants, we don't know what type they'll be used as, so
we just emit them as uint, and then bitcast them to whatever we need.
But this isn't a good idea for ConstOffset, which needs to actually be a
const value, and not a const value bitcasted. So we sadly have to
open-code the const emitting here to avoid the problem.
Fixes: e963d35efe ("zink: use ConstOffset for nir_tex_src_offset")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4831
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11032>
(cherry picked from commit 7613837206)
For fragment shaders that only contain a discard, the exec mask has
to be zero'd and everything discarded.
It seems unnecessary to emit an export here because if the FS has no
exports, the compiler already emits a null export at the end.
Fixes incorrect hair rendering in Detroit: Become Human.
fossil-db (Sienna Cichlid):
Totals from 3 (0.00% of 149839) affected shaders:
CodeSize: 2896 -> 2872 (-0.83%)
Instrs: 556 -> 553 (-0.54%)
Latency: 29266 -> 29214 (-0.18%)
InvThroughput: 3374 -> 3372 (-0.06%)
Cc: 21.1 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10955>
(cherry picked from commit 729ebe4b17)
Note that CCS isn't ambiguated during a HiZ ambiguate. Dumping the CCS
surface after a HiZ ambiguate shows that the CCS is unchanged.
Fixes: 98dc7f56b7 ("intel/isl: Add a separate ISL_AUX_USAGE_HIZ_CCS_WT")
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9112>
(cherry picked from commit 19a8bd4c63)
We previously allocated only 16MB, but this isn't always enough. Now
that we have growable (heap) on recent kernels, there's not much reason
to try to shrink this allocation.
Fixes OUT_OF_MEMORY fault on furmark trace.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10938>
(cherry picked from commit ac1ee2bebe)
Fallback to a slow clear, this could be improved by splitting the
clear into two parts (one fast and one slow) but that's complicated.
Cc: 21.1 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10516>
(cherry picked from commit e98c61e9f3)
This patch will avoid reallocation,if surface is already protected.
Fixing the comparision logic of boolean value(true \ flase) with
PIPE_BIND_PROTECTED.
Fixes: 81be8b3c2f ("va/picture: make sure destination buffer is protected if needed")
Signed-off-by: SureshGuttula <suresh.guttula@amd.corp-partner.google.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10916>
(cherry picked from commit 0236b8a5de)
this was broken for the indirect case if the indirect draw count or
firstIndex was nonzero and also would rewrite the index buffer onto the
wrong offset of the dst buffer
Fixes: 0c85d6c523 ("gallium/util: factor out primitive-restart rewriting logic")
Fixes: 330d0607ed ("gallium: remove pipe_index_buffer and set_index_buffer")
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10909>
(cherry picked from commit 1272c2e052)
According to isl_gfx7.c:264, the display engine does not support Y
tiled buffers prior to Skylake. But we exposed I915_FORMAT_MOD_Y_TILED
even when querying for a list of modifiers with PIPE_BIND_SCANOUT set,
which we can't support. That led to crashes later when we tried to
create such an image, and isl rightly denied it.
Fixes crashes in wflinfo since c03e79d783, but the bug exists before
that and it's probably worth a stable backport even without that patch.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4815
Fixes: c03e79d783 ("loader/dri: hook up createImageWithModifiers2")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10907>
(cherry picked from commit dd508b2bed)
According to isl_gfx7.c:264, the display engine does not support Y
tiled buffers prior to Skylake. But we exposed I915_FORMAT_MOD_Y_TILED
even when querying for a list of modifiers with __DRI_IMAGE_USE_SCANOUT
set, which we can't support. That led to crashes later when we tried
to create such an image, and isl rightly denied it.
This duplicates a bit of code from ISL, but the isl_gfx6_filter_tiling
function that we ought to use to filter things relies on surf_info,
which we don't have at this stage. This is probably good enough.
Fixes crashes in wflinfo since c03e79d783, but the bug exists before
that and it's probably worth a stable backport even without that patch.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4815
Fixes: c03e79d783 ("loader/dri: hook up createImageWithModifiers2")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10907>
(cherry picked from commit e9e953ff94)
This hardware can't do any form of indirect addressing. The couple of new
Crashes are the backend falling over when faced with loops/ifs.
Fixes: 8a22064d31 ("i915g: Implement vertex textures.")
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10874>
(cherry picked from commit 8b0901c707)
The 3D-pipeline fast clears try to emit FS constants before an FS is
necessarily bound, causing segfaults in dEQP. Plus it flushes the whole
batchbuffer so it'll probably be slower anyway.
Fixes: 6358e6371b ("i915g: implement hw clear")
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10874>
(cherry picked from commit 8509aceb74)
ds_swizzle_b32 requires a VGPR and DPP can't encode SGPR sources.
Fixes
dEQP-VK.graphicsfuzz.cov-derivative-uniform-vector-global-loop-count.
Cc: 21.1 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10840>
(cherry picked from commit fe2a5716ee)
When most of these patterns were created, we believed, incorrectly, that
fsat(NaN) was NaN. We have since realized that fsat(NaN) is zero.
Originally, this changed the patterns to use is_a_number. This didn't
help any shaders, so it's easier to just drop the optimizations.
This commit crossed paths with 4c3ad4d065 ("nir/algebraic: mark more
optimization with fsat(NaN) as inexact") and bc123c396a
("nir/algebraic: mark some optimizations with fsat(NaN) as inexact").
Given that these don't impact very many shaders, it seems safer to just
remove them.
As discussed in
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8716, I tried
modifying these patterns to use !(b cmp a). Unfortunately, on Intel
GPUs, the results were much worse than just removing the patterns
altogether.
Some other related patterns will be addressed in later commits.
There are still a number of patterns that use the identity fsat(1-X) ==
1 - fsat(X). If X is NaN, the former is zero while the latter is 1.0.
I haven't evaluted these patterns yet. If changes are needed in these
patterns, it should be a separate commit anyway.
v2: Replace arrow `=>` with `->` in comments because the `=>` looks a
lot like `<=` comparison. Suggested by Rhys.
Fixes: 92b75c126b ("nir/algebraic: Replace checks that a value is between (or not) [0, 1]")
Fixes: a7f0c57673 ("nir/algebraic: Eliminate useless fsat() on operand of comparison w/value in (0, 1)")
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
All Intel hardware had similar results. (Ice Lake shown)
total instructions in shared programs: 20029060 -> 20029670 (<.01%)
instructions in affected programs: 69236 -> 69846 (0.88%)
helped: 0
HURT: 263
HURT stats (abs) min: 1 max: 20 x̄: 2.32 x̃: 1
HURT stats (rel) min: 0.30% max: 11.11% x̄: 1.35% x̃: 0.98%
95% mean confidence interval for instructions value: 1.86 2.78
95% mean confidence interval for instructions %-change: 1.18% 1.52%
Instructions are HURT.
total cycles in shared programs: 979821278 -> 979834425 (<.01%)
cycles in affected programs: 1476848 -> 1489995 (0.89%)
helped: 49
HURT: 204
helped stats (abs) min: 1 max: 812 x̄: 102.31 x̃: 20
helped stats (rel) min: 0.01% max: 21.43% x̄: 2.23% x̃: 0.52%
HURT stats (abs) min: 2 max: 2600 x̄: 89.02 x̃: 16
HURT stats (rel) min: 0.04% max: 27.27% x̄: 1.49% x̃: 0.72%
95% mean confidence interval for cycles value: 13.18 90.75
95% mean confidence interval for cycles %-change: 0.29% 1.25%
Cycles are HURT.
No fossil-db changes.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10012>
(cherry picked from commit d69ba58644)
Caught this with an LTO build:
[1465/1465] Linking target src/gallium/targets/dri/libgallium_dri.so
In function ‘spirv_shader_delete’,
inlined from ‘nir_to_spirv’ at ../src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c:3907:7:
../src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c:3916:4: warning: ‘free’ called on pointer ‘block_1394’ with nonzero offset 48 [-Wfree-nonheap-object]
3916 | FREE(s);
| ^
../src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c: In function ‘nir_to_spirv’:
../src/util/ralloc.c:133:18: note: returned from ‘malloc’
133 | void *block = malloc(align64(size + sizeof(ralloc_header),
| ^
Since s->words is allocated on the same ralloc context we can simplify
further by freeing the context all at once.
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10754>
(cherry picked from commit 584145ea88)
The way we handle spilling for fp64 in vec4 is to emit a series of MOVs
which swizzles the data around and then a pair of 32-bit spills. This
works great except that the next time we go to pick a spill reg, the
compiler isn't smart enough to figure out that the register has already
been spilled. Normally we do this by looking at the sources of spill
instructions (or destinations of fills) but, because it's separated from
the actual value by a MOV, we can't see it. This commit adds a new
opcode VEC4_OPCODE_MOV_FOR_SCRATCH which is identical to MOV in
semantics except that it lets RA know not to spill again.
Fixes: 82c69426a5 "i965/vec4: support basic spilling of 64-bit registers"
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10571>
(cherry picked from commit 2db8867943)
