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compiler/spirv: expand_to_vec4 -> nir_pad_vec4
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10821>
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0f8fef1261
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1199d86b2c
1 changed files with 3 additions and 20 deletions
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@ -3091,29 +3091,12 @@ fill_common_atomic_sources(struct vtn_builder *b, SpvOp opcode,
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}
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}
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static nir_ssa_def *
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expand_to_vec4(nir_builder *b, nir_ssa_def *value)
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{
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nir_ssa_def *components[4];
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if (value->num_components == 4)
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return value;
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nir_ssa_def *undef = nir_ssa_undef(b, 1, value->bit_size);
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for (unsigned i = 0; i < 4; i++) {
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if (i < value->num_components)
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components[i] = nir_channel(b, value, i);
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else
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components[i] = undef;
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}
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return nir_vec(b, components, 4);
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}
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static nir_ssa_def *
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get_image_coord(struct vtn_builder *b, uint32_t value)
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{
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nir_ssa_def *coord = vtn_get_nir_ssa(b, value);
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/* The image_load_store intrinsics assume a 4-dim coordinate */
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return expand_to_vec4(&b->nb, coord);
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return nir_pad_vec4(&b->nb, coord);
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}
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static void
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@ -3337,7 +3320,7 @@ vtn_handle_image(struct vtn_builder *b, SpvOp opcode,
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/* The image coordinate is always 4 components but we may not have that
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* many. Swizzle to compensate.
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*/
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intrin->src[1] = nir_src_for_ssa(expand_to_vec4(&b->nb, image.coord));
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intrin->src[1] = nir_src_for_ssa(nir_pad_vec4(&b->nb, image.coord));
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intrin->src[2] = nir_src_for_ssa(image.sample);
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break;
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}
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@ -3387,7 +3370,7 @@ vtn_handle_image(struct vtn_builder *b, SpvOp opcode,
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/* nir_intrinsic_image_deref_store always takes a vec4 value */
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assert(op == nir_intrinsic_image_deref_store);
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intrin->num_components = 4;
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intrin->src[3] = nir_src_for_ssa(expand_to_vec4(&b->nb, value->def));
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intrin->src[3] = nir_src_for_ssa(nir_pad_vec4(&b->nb, value->def));
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/* Only OpImageWrite can support a lod parameter if
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* SPV_AMD_shader_image_load_store_lod is used but the current NIR
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* intrinsics definition for atomics requires us to set it for
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