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radv: add radv_absolute_depth_bias

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Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10980>
This commit is contained in:
Rhys Perry 2021-05-24 16:23:59 +01:00 • committed by Marge Bot
parent ceb7225057
commit 665f11e829
3 changed files with 28 additions and 21 deletions
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44
src/amd/vulkan/radv_device.c
View file

@ -882,6 +882,9 @@ radv_handle_per_app_options(struct radv_instance *instance, const VkApplicationI
instance->disable_shrink_image_store =
driQueryOptionb(&instance->dri_options, "radv_disable_shrink_image_store");
instance->absolute_depth_bias =
driQueryOptionb(&instance->dri_options, "radv_absolute_depth_bias");
if (driQueryOptionb(&instance->dri_options, "radv_no_dynamic_bounds"))
instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
}
@ -892,7 +895,7 @@ static const driOptionDescription radv_dri_options[] = {
DRI_CONF_VK_X11_ENSURE_MIN_IMAGE_COUNT(false) DRI_CONF_RADV_REPORT_LLVM9_VERSION_STRING(false)
DRI_CONF_RADV_ENABLE_MRT_OUTPUT_NAN_FIXUP(false)
DRI_CONF_RADV_DISABLE_SHRINK_IMAGE_STORE(false) DRI_CONF_RADV_NO_DYNAMIC_BOUNDS(false)
DRI_CONF_RADV_OVERRIDE_UNIFORM_OFFSET_ALIGNMENT(0) DRI_CONF_SECTION_END
DRI_CONF_RADV_ABSOLUTE_DEPTH_BIAS(false) DRI_CONF_RADV_OVERRIDE_UNIFORM_OFFSET_ALIGNMENT(0) DRI_CONF_SECTION_END
DRI_CONF_SECTION_DEBUG DRI_CONF_OVERRIDE_VRAM_SIZE()
DRI_CONF_VK_WSI_FORCE_BGRA8_UNORM_FIRST(false) DRI_CONF_SECTION_END};
@ -6681,32 +6684,31 @@ radv_initialise_ds_surface(struct radv_device *device, struct radv_ds_buffer_inf
unsigned level = iview->base_mip;
unsigned format, stencil_format;
uint64_t va, s_offs, z_offs;
bool stencil_only = false;
bool stencil_only = iview->image->vk_format == VK_FORMAT_S8_UINT;
const struct radv_image_plane *plane = &iview->image->planes[0];
const struct radeon_surf *surf = &plane->surface;
assert(vk_format_get_plane_count(iview->image->vk_format) == 1);
memset(ds, 0, sizeof(*ds));
switch (iview->image->vk_format) {
case VK_FORMAT_D24_UNORM_S8_UINT:
case VK_FORMAT_X8_D24_UNORM_PACK32:
ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
break;
case VK_FORMAT_D16_UNORM:
case VK_FORMAT_D16_UNORM_S8_UINT:
ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
break;
case VK_FORMAT_D32_SFLOAT:
case VK_FORMAT_D32_SFLOAT_S8_UINT:
ds->pa_su_poly_offset_db_fmt_cntl =
S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) | S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
break;
case VK_FORMAT_S8_UINT:
stencil_only = true;
break;
default:
break;
if (!device->instance->absolute_depth_bias) {
switch (iview->image->vk_format) {
case VK_FORMAT_D24_UNORM_S8_UINT:
case VK_FORMAT_X8_D24_UNORM_PACK32:
ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
break;
case VK_FORMAT_D16_UNORM:
case VK_FORMAT_D16_UNORM_S8_UINT:
ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
break;
case VK_FORMAT_D32_SFLOAT:
case VK_FORMAT_D32_SFLOAT_S8_UINT:
ds->pa_su_poly_offset_db_fmt_cntl =
S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) | S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
break;
default:
break;
}
}
format = radv_translate_dbformat(iview->image->vk_format);

1
src/amd/vulkan/radv_private.h
View file

@ -327,6 +327,7 @@ struct radv_instance {
bool enable_mrt_output_nan_fixup;
bool disable_tc_compat_htile_in_general;
bool disable_shrink_image_store;
bool absolute_depth_bias;
};
VkResult radv_init_wsi(struct radv_physical_device *physical_device);

4
src/util/driconf.h
View file

@ -481,6 +481,10 @@
DRI_CONF_OPT_B(radv_disable_shrink_image_store, def, \
"Disabling shrinking of image stores based on the format")
#define DRI_CONF_RADV_ABSOLUTE_DEPTH_BIAS(def) \
DRI_CONF_OPT_B(radv_absolute_depth_bias, def, \
"Consider depthBiasConstantFactor an absolute depth bias (like D3D9)")
#define DRI_CONF_RADV_OVERRIDE_UNIFORM_OFFSET_ALIGNMENT(def) \
DRI_CONF_OPT_I(radv_override_uniform_offset_alignment, def, 0, 128, \
"Override the minUniformBufferOffsetAlignment exposed to the application. (0 = default)")