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aco: fix derivatives/intrinsics with SGPR sources

Browse source 
ds_swizzle_b32 requires a VGPR and DPP can't encode SGPR sources.

Fixes
dEQP-VK.graphicsfuzz.cov-derivative-uniform-vector-global-loop-count.

Cc: 21.1 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10840>
(cherry picked from commit fe2a5716ee)
This commit is contained in:
Samuel Pitoiset 2021-05-17 15:21:13 +02:00 • committed by Eric Engestrom
parent 29874d55d5
commit f61539457c
2 changed files with 17 additions and 2 deletions
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2
.pick_status.json
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@ -1381,7 +1381,7 @@
"description": "aco: fix derivatives/intrinsics with SGPR sources",
"nominated": true,
"nomination_type": 0,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": null
},

17
src/amd/compiler/aco_instruction_selection.cpp
View file

@ -3230,7 +3230,7 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
case nir_op_fddy_fine:
case nir_op_fddx_coarse:
case nir_op_fddy_coarse: {
Temp src = get_alu_src(ctx, instr->src[0]);
Temp src = as_vgpr(ctx, get_alu_src(ctx, instr->src[0]));
uint16_t dpp_ctrl1, dpp_ctrl2;
if (instr->op == nir_op_fddx_fine) {
dpp_ctrl1 = dpp_quad_perm(0, 0, 2, 2);
@ -7993,6 +7993,10 @@ void visit_intrinsic(isel_context *ctx, nir_intrinsic_instr *instr)
if (instr->intrinsic == nir_intrinsic_read_invocation || !nir_src_is_divergent(instr->src[1]))
tid = bld.as_uniform(tid);
Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
if (instr->dest.ssa.bit_size != 1)
src = as_vgpr(ctx, src);
if (src.regClass() == v1b || src.regClass() == v2b) {
Temp tmp = bld.tmp(v1);
tmp = emit_wqm(bld, emit_bpermute(ctx, bld, tid, src), tmp);
@ -8166,6 +8170,9 @@ void visit_intrinsic(isel_context *ctx, nir_intrinsic_instr *instr)
unsigned lane = nir_src_as_const_value(instr->src[1])->u32;
uint32_t dpp_ctrl = dpp_quad_perm(lane, lane, lane, lane);
if (instr->dest.ssa.bit_size != 1)
src = as_vgpr(ctx, src);
if (instr->dest.ssa.bit_size == 1) {
assert(src.regClass() == bld.lm);
assert(dst.regClass() == bld.lm);
@ -8243,6 +8250,10 @@ void visit_intrinsic(isel_context *ctx, nir_intrinsic_instr *instr)
dpp_ctrl |= (1 << 15);
Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
if (instr->dest.ssa.bit_size != 1)
src = as_vgpr(ctx, src);
if (instr->dest.ssa.bit_size == 1) {
assert(src.regClass() == bld.lm);
src = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), Operand((uint32_t)-1), src);
@ -8298,6 +8309,10 @@ void visit_intrinsic(isel_context *ctx, nir_intrinsic_instr *instr)
}
Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
uint32_t mask = nir_intrinsic_swizzle_mask(instr);
if (instr->dest.ssa.bit_size != 1)
src = as_vgpr(ctx, src);
if (instr->dest.ssa.bit_size == 1) {
assert(src.regClass() == bld.lm);
src = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), Operand((uint32_t)-1), src);