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mesa/src/intel/compiler
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Rohan Garg e103afe7be
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brw: run the nir_opt_offsets pass and set the maximum offset size 
Perf A/B testing on DG2: no changes
Perf A/B testing on BMG: +2.1% Blackops3, +1.5% Cyberpunk

DG2 stats (mostly insignificant):
Assassins Creed Valhalla:
 Totals from 1169 (55.67% of 2100) affected shaders:
 Instrs: 509237 -> 509215 (-0.00%)
 Cycle count: 30614325 -> 30607419 (-0.02%); split: -0.03%, +0.00%
 Non SSA regs after NIR: 83434 -> 85909 (+2.97%)

Blackops 3:
 Totals from 1045 (64.63% of 1617) affected shaders:
 Instrs: 527312 -> 527310 (-0.00%)
 Cycle count: 496912222 -> 496902846 (-0.00%); split: -0.00%, +0.00%
 Non SSA regs after NIR: 106883 -> 109095 (+2.07%)

Cyberpunk:
 Totals from 706 (56.03% of 1260) affected shaders:
 Instrs: 345976 -> 345974 (-0.00%); split: -0.00%, +0.00%
 Cycle count: 9775138 -> 9775472 (+0.00%); split: -0.00%, +0.00%
 Max live registers: 40295 -> 40297 (+0.00%)
 Non SSA regs after NIR: 93245 -> 94718 (+1.58%)

Fortnite:
 Totals from 4210 (55.98% of 7521) affected shaders:
 Instrs: 2205471 -> 2205469 (-0.00%)
 Cycle count: 91451040 -> 91450956 (-0.00%); split: -0.00%, +0.00%
 Non SSA regs after NIR: 952354 -> 961664 (+0.98%)

LNL stats (notable changes):
Assassins Creed Valhalla:
 Totals from 1684 (83.57% of 2015) affected shaders:
 Instrs: 774305 -> 764501 (-1.27%); split: -1.27%, +0.01%
 Cycle count: 58845842 -> 58699250 (-0.25%); split: -0.98%, +0.73%
 Spill count: 625 -> 638 (+2.08%)
 Fill count: 1490 -> 1503 (+0.87%)
 Scratch Memory Size: 41984 -> 44032 (+4.88%)
 Max live registers: 196424 -> 197561 (+0.58%); split: -0.10%, +0.68%

Blackops 3:
 Totals from 1125 (76.53% of 1470) affected shaders:
 Instrs: 781749 -> 773275 (-1.08%); split: -1.08%, +0.00%
 Subgroup size: 22896 -> 22912 (+0.07%)
 Cycle count: 659864454 -> 654641032 (-0.79%); split: -1.10%, +0.31%
 Max live registers: 116772 -> 116854 (+0.07%); split: -0.01%, +0.08%
 Non SSA regs after NIR: 172648 -> 168260 (-2.54%); split: -2.55%, +0.01%

Control:
 Totals from 378 (51.50% of 734) affected shaders:
 Instrs: 148184 -> 147544 (-0.43%)
 Cycle count: 6905200 -> 6913366 (+0.12%); split: -0.30%, +0.42%
 Max live registers: 41271 -> 41281 (+0.02%)
 Non SSA regs after NIR: 44964 -> 43868 (-2.44%); split: -2.45%, +0.01%

Cyberpunk:
 Totals from 1141 (92.46% of 1234) affected shaders:
 Instrs: 636744 -> 629333 (-1.16%)
 Subgroup size: 24256 -> 24272 (+0.07%)
 Cycle count: 24952258 -> 24801298 (-0.60%); split: -1.39%, +0.78%
 Max live registers: 125848 -> 126855 (+0.80%); split: -0.00%, +0.80%
 Non SSA regs after NIR: 127399 -> 119837 (-5.94%); split: -5.95%, +0.02%

Fortnite:
 Totals from 5497 (83.52% of 6582) affected shaders:
 Instrs: 4072831 -> 4041852 (-0.76%); split: -0.77%, +0.01%
 Subgroup size: 103296 -> 103312 (+0.02%)
 Cycle count: 133046874 -> 132789242 (-0.19%); split: -0.67%, +0.48%
 Spill count: 7218 -> 7254 (+0.50%); split: -0.33%, +0.83%
 Fill count: 11724 -> 11749 (+0.21%); split: -0.34%, +0.55%
 Scratch Memory Size: 591872 -> 599040 (+1.21%)
 Max live registers: 816530 -> 818522 (+0.24%); split: -0.01%, +0.26%
 Non SSA regs after NIR: 1610296 -> 1560284 (-3.11%); split: -3.11%, +0.00%

Hitman3:
 Totals from 4713 (92.39% of 5101) affected shaders:
 Instrs: 2731598 -> 2698224 (-1.22%)
 Cycle count: 186422098 -> 185472640 (-0.51%); split: -1.12%, +0.61%
 Spill count: 3244 -> 3242 (-0.06%)
 Fill count: 9937 -> 9933 (-0.04%)
 Max live registers: 585035 -> 589801 (+0.81%); split: -0.00%, +0.82%
 Non SSA regs after NIR: 347681 -> 324314 (-6.72%); split: -6.73%, +0.01%

Hogwarts Legacy:
 Totals from 930 (59.81% of 1555) affected shaders:
 Instrs: 464146 -> 459526 (-1.00%); split: -1.00%, +0.01%
 Subgroup size: 19104 -> 19120 (+0.08%)
 Cycle count: 24062460 -> 24078964 (+0.07%); split: -0.49%, +0.56%
 Spill count: 2068 -> 1964 (-5.03%); split: -5.22%, +0.19%
 Fill count: 2342 -> 2205 (-5.85%); split: -6.40%, +0.56%
 Scratch Memory Size: 147456 -> 141312 (-4.17%)
 Max live registers: 112384 -> 112787 (+0.36%); split: -0.08%, +0.44%
 Non SSA regs after NIR: 80293 -> 79161 (-1.41%); split: -1.72%, +0.32%

Metro Exodus:
 Totals from 29755 (78.62% of 37846) affected shaders:
 Instrs: 11495578 -> 11492951 (-0.02%); split: -0.02%, +0.00%
 Subgroup size: 644688 -> 644704 (+0.00%)
 Cycle count: 301572068 -> 301548054 (-0.01%); split: -0.03%, +0.02%
 Max live registers: 3369504 -> 3370454 (+0.03%); split: -0.00%, +0.03%
 Non SSA regs after NIR: 2476561 -> 2396090 (-3.25%); split: -3.27%, +0.02%

Red Dead Redemption 2:
 Totals from 4161 (78.61% of 5293) affected shaders:
 Instrs: 2428782 -> 2409032 (-0.81%); split: -0.82%, +0.00%
 Subgroup size: 85344 -> 85360 (+0.02%)
 Cycle count: 8514984142 -> 8533415324 (+0.22%); split: -0.02%, +0.23%
 Spill count: 4659 -> 4674 (+0.32%); split: -0.02%, +0.34%
 Fill count: 11236 -> 11231 (-0.04%); split: -0.19%, +0.14%
 Scratch Memory Size: 398336 -> 397312 (-0.26%)
 Max live registers: 473946 -> 475798 (+0.39%); split: -0.08%, +0.47%
 Non SSA regs after NIR: 616820 -> 567706 (-7.96%); split: -8.09%, +0.12%

Rise Of The Tomb Raider:
 Totals from 68 (46.58% of 146) affected shaders:
 Instrs: 28209 -> 27801 (-1.45%)
 Subgroup size: 1584 -> 1600 (+1.01%)
 Cycle count: 16182992 -> 16249364 (+0.41%); split: -0.97%, +1.38%
 Max live registers: 7320 -> 7296 (-0.33%); split: -0.38%, +0.05%
 Non SSA regs after NIR: 8438 -> 8207 (-2.74%); split: -2.82%, +0.08%

Spiderman Remastered:
 Totals from 6403 (93.87% of 6821) affected shaders:
 Instrs: 5662713 -> 5597949 (-1.14%); split: -1.28%, +0.14%
 Cycle count: 282861519016 -> 279806958122 (-1.08%); split: -1.26%, +0.18%
 Spill count: 61150 -> 60754 (-0.65%); split: -1.13%, +0.48%
 Fill count: 162597 -> 163190 (+0.36%); split: -0.84%, +1.21%
 Scratch Memory Size: 5834752 -> 5804032 (-0.53%); split: -0.70%, +0.18%
 Max live registers: 901926 -> 903820 (+0.21%); split: -0.01%, +0.22%
 Non SSA regs after NIR: 555053 -> 521016 (-6.13%); split: -6.14%, +0.01%

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35252>
2025-06-22 10:55:24 +00:00
..
elk intel/elk: Move wpos_w setup right into nir_intrinsic_load_frag_w. 2025-06-18 23:11:43 +00:00
tests brw: Rename shared function enums for clarity 2025-02-27 08:49:24 +00:00
brw_analysis.cpp brw: Make brw_range use half-open ranges 2025-04-09 19:06:49 +00:00
brw_analysis.h brw: Track the largest VGRF size in liveness analysis 2025-04-11 20:34:51 +00:00
brw_analysis_def.cpp brw: Add basic infrastructure for load_reg pseudo op 2025-04-04 06:45:02 +00:00
brw_analysis_liveness.cpp brw: Track the largest VGRF size in liveness analysis 2025-04-11 20:34:51 +00:00
brw_analysis_performance.cpp intel/compiler: Add support for MSAA typed load/store messages 2025-03-07 23:06:14 +00:00
brw_asm.c brw: Rework label tracking in assembler 2025-03-06 17:06:20 -08:00
brw_asm.h brw: Fix size in assembler when compacting 2025-03-03 20:43:56 +00:00
brw_asm_internal.h brw: Rework label tracking in assembler 2025-03-06 17:06:20 -08:00
brw_asm_tool.c intel/compiler: fix lingering i965 references 2025-04-03 03:17:25 +00:00
brw_builder.cpp brw: Add brw_builder::uniform() 2025-04-04 23:07:21 +00:00
brw_builder.h brw: Add brw_builder::uniform() 2025-04-04 23:07:21 +00:00
brw_cfg.cpp brw: Remove adjust_block_ips and brw_inst::remove() with defer 2025-03-29 00:25:51 +00:00
brw_cfg.h brw: Remove adjust_block_ips and brw_inst::remove() with defer 2025-03-29 00:25:51 +00:00
brw_compile_bs.cpp intel/debug: shader dump filter 2025-05-23 19:57:02 +00:00
brw_compile_cs.cpp intel/debug: shader dump filter 2025-05-23 19:57:02 +00:00
brw_compile_fs.cpp intel/elk: Save the UW pixel x/y as a temp. 2025-06-18 23:11:38 +00:00
brw_compile_gs.cpp intel/debug: shader dump filter 2025-05-23 19:57:02 +00:00
brw_compile_mesh.cpp intel/debug: shader dump filter 2025-05-23 19:57:02 +00:00
brw_compile_tcs.cpp intel/debug: shader dump filter 2025-05-23 19:57:02 +00:00
brw_compile_tes.cpp intel/debug: shader dump filter 2025-05-23 19:57:02 +00:00
brw_compile_vs.cpp intel/debug: shader dump filter 2025-05-23 19:57:02 +00:00
brw_compiler.c intel: Use the common NIR lowering for fquantize2f16. 2025-06-18 22:45:08 +00:00
brw_compiler.h brw: implement read without format lowering 2025-06-06 12:28:42 +00:00
brw_debug_recompile.c intel/brw: Simplify @file annotations 2024-07-22 22:48:03 +00:00
brw_device_sha1_gen_c.py intel/compiler: drop unused ray-tracing fields from cache hash 2024-03-22 00:01:28 +00:00
brw_disasm.c brw/disasm: Don't print src1 information for SEND gather 2025-06-03 22:52:39 +00:00
brw_disasm.h intel/brw: support for dumping shader line numbers 2025-04-08 19:39:53 +00:00
brw_disasm_info.cpp intel/brw: support for dumping shader line numbers 2025-04-08 19:39:53 +00:00
brw_disasm_info.h intel/brw: Rename fs_inst to brw_inst 2025-01-31 00:57:21 +00:00
brw_disasm_tool.c intel/brw: Remove Gfx8- code from disassembler 2024-02-28 05:45:38 +00:00
brw_eu.c intel/compiler: fix SHA generation for shader replace 2025-05-27 22:57:19 +00:00
brw_eu.h brw: encode the offset into the message descriptor for Xe2 2025-06-22 10:55:24 +00:00
brw_eu_compact.c brw: Add support for GOTO/JOIN in the assembler 2025-03-06 17:06:20 -08:00
brw_eu_defines.h brw: introduce MEMORY_LOGICAL_ADDRESS_OFFSET to encode address offsets 2025-06-22 10:55:24 +00:00
brw_eu_emit.c brw: encode the offset into the message descriptor for Xe2 2025-06-22 10:55:24 +00:00
brw_eu_inst.h brw: Add BRW_TYPE_BF for bfloat16 2025-03-25 05:23:37 +00:00
brw_eu_validate.c brw: Update EU validation to allow packed BF mixed with packed F 2025-04-14 18:23:43 +00:00
brw_from_nir.cpp brw: store the buffer offset for load/store intrinsics 2025-06-22 10:55:24 +00:00
brw_generator.cpp brw: encode the offset into the message descriptor for Xe2 2025-06-22 10:55:24 +00:00
brw_generator.h brw: factor out base prog_data setting 2025-02-22 08:30:22 +00:00
brw_gram.y brw: Add EU assembler support for bfloat16 2025-03-25 05:23:37 +00:00
brw_inst.cpp brw: Consider bfloat16 in lower regioning pass 2025-04-29 16:29:37 +00:00
brw_inst.h brw: encode the offset into the message descriptor for Xe2 2025-06-22 10:55:24 +00:00
brw_isa_info.h intel/compiler: Use #pragma once instead of header guards 2024-12-11 19:47:44 +00:00
brw_kernel.c treewide: Switch to nir_progress 2025-02-26 15:19:53 +00:00
brw_kernel.h intel: rework CL pre-compile 2025-01-25 03:28:07 +00:00
brw_lex.l brw: Add EU assembler support for bfloat16 2025-03-25 05:23:37 +00:00
brw_load_reg.cpp brw: Add passes to generate and lower load_reg 2025-04-04 06:45:02 +00:00
brw_lower.cpp intel/compiler: Centralize type stomping logic for Gen12.5 restrictions 2025-05-22 06:46:18 +00:00
brw_lower_dpas.cpp brw: Simplify brw_builder "insert before inst" constructor 2025-03-06 23:33:38 +00:00
brw_lower_integer_multiplication.cpp brw: Remove bblock_t parameters from various passes 2025-03-06 23:33:38 +00:00
brw_lower_logical_sends.cpp brw: encode the offset into the message descriptor for Xe2 2025-06-22 10:55:24 +00:00
brw_lower_pack.cpp brw: Simplify brw_builder "insert before inst" constructor 2025-03-06 23:33:38 +00:00
brw_lower_regioning.cpp brw: Consider bfloat16 in lower regioning pass 2025-04-29 16:29:37 +00:00
brw_lower_scoreboard.cpp brw: Use brw_range::last() to explicit get the last valid IP 2025-04-09 19:06:49 +00:00
brw_lower_simd_width.cpp brw/nir: add intrinsics to read attribute payload register indirectly 2025-05-08 06:48:35 +00:00
brw_lower_subgroup_ops.cpp brw: Add brw_builder::uniform() 2025-04-04 23:07:21 +00:00
brw_nir.c brw: run the nir_opt_offsets pass and set the maximum offset size 2025-06-22 10:55:24 +00:00
brw_nir.h brw: run the nir_opt_offsets pass and set the maximum offset size 2025-06-22 10:55:24 +00:00
brw_nir_analyze_ubo_ranges.c intel/compiler: take reg_unit size into account with ubo ranges 2025-01-07 21:38:06 +00:00
brw_nir_lower_alpha_to_coverage.c brw/nir: use a new intrinsic for fs_msaa_flag 2025-05-08 06:48:34 +00:00
brw_nir_lower_cooperative_matrix.c intel: Add support for BFloat16 as cooperative matrix source 2025-04-29 16:29:37 +00:00
brw_nir_lower_cs_intrinsics.c treewide: Switch to nir_progress 2025-02-26 15:19:53 +00:00
brw_nir_lower_fs_barycentrics.c brw: add lowering passes for FS barycentric inputs 2025-05-20 20:57:59 +00:00
brw_nir_lower_fs_msaa.c brw/anv: add provoking vertex to fs_msaa_flags 2025-05-20 20:57:58 +00:00
brw_nir_lower_fsign.py intel/brw: Use range analysis to optimize fsign 2024-05-14 01:28:21 +00:00
brw_nir_lower_immediate_offsets.c brw: run the nir_opt_offsets pass and set the maximum offset size 2025-06-22 10:55:24 +00:00
brw_nir_lower_intersection_shader.c intel/compiler: Update MemRay data structure to 64-bit 2025-04-21 20:10:45 +00:00
brw_nir_lower_ray_queries.c intel/rt: Update BVH instance leaf load for Xe3+ 2025-04-21 20:10:45 +00:00
brw_nir_lower_rt_intrinsics.c anv/brw: stop turning load_push_constants into load_uniform 2025-05-22 07:49:20 +00:00
brw_nir_lower_rt_intrinsics_pre_trace.c brw: add pre ray trace intrinsic moves 2025-05-06 13:34:53 +00:00
brw_nir_lower_sample_index_in_coord.c intel/compiler: Lower sample index into coord for MSRT messages 2025-03-07 23:06:14 +00:00
brw_nir_lower_shader_calls.c intel/compiler: provide a helper for null any-hit shader 2025-05-20 10:58:53 +00:00
brw_nir_lower_storage_image.c brw: implement read without format lowering 2025-06-06 12:28:42 +00:00
brw_nir_lower_texel_address.c intel/compiler: Use correct enum type 2025-03-13 20:11:10 +00:00
brw_nir_lower_texture.c brw: move texture offset packing to NIR 2025-03-29 02:15:18 +00:00
brw_nir_opt_fsat.c treewide: Switch to nir_progress 2025-02-26 15:19:53 +00:00
brw_nir_rt.c intel/compiler/rt: Calculate barycentrics on demand 2025-04-21 20:10:45 +00:00
brw_nir_rt.h intel/compiler: provide a helper for null any-hit shader 2025-05-20 10:58:53 +00:00
brw_nir_rt_builder.h intel/rt: Update BVH instance leaf load for Xe3+ 2025-04-21 20:10:45 +00:00
brw_nir_trig_workarounds.py
brw_opt.cpp intel/compiler: Centralize type stomping logic for Gen12.5 restrictions 2025-05-22 06:46:18 +00:00
brw_opt_address_reg_load.cpp brw: Add brw_builder::uniform() 2025-04-04 23:07:21 +00:00
brw_opt_algebraic.cpp brw/algebraic: Convert some NOT to MOV 2025-04-28 19:44:23 +00:00
brw_opt_bank_conflicts.cpp intel/brw: Rename fs_visitor to brw_shader 2025-02-11 09:13:28 +00:00
brw_opt_cmod_propagation.cpp brw/cmod: Allow integer CMP to ADD propagation only for Z and NZ 2025-04-28 19:44:23 +00:00
brw_opt_combine_constants.cpp brw: Use brw_inst::block in Combine Constants 2025-03-06 23:33:38 +00:00
brw_opt_copy_propagation.cpp brw: Consider bfloat16 in copy propagation 2025-04-29 16:29:37 +00:00
brw_opt_cse.cpp brw: make HALT instruction act as barrier in new CSE pass 2025-04-29 20:28:24 +00:00
brw_opt_dead_code_eliminate.cpp brw: Remove adjust_block_ips and brw_inst::remove() with defer 2025-03-29 00:25:51 +00:00
brw_opt_register_coalesce.cpp brw: don't generate invalid instructions 2025-06-04 06:08:26 +00:00
brw_opt_saturate_propagation.cpp brw: Clean up saturate propagation after non-defs version removal 2025-04-09 19:06:48 +00:00
brw_opt_txf_combiner.cpp brw: Simplify brw_builder "insert before inst" constructor 2025-03-06 23:33:38 +00:00
brw_opt_virtual_grfs.cpp brw: Don't assert about MAX_VGRF_SIZE in brw_opt_split_virtual_grfs() 2025-04-11 20:34:51 +00:00
brw_packed_float.c
brw_prim.h intel/compiler: Use #pragma once instead of header guards 2024-12-11 19:47:44 +00:00
brw_print.cpp brw: encode the offset into the message descriptor for Xe2 2025-06-22 10:55:24 +00:00
brw_private.h intel/debug: shader dump filter 2025-05-23 19:57:02 +00:00
brw_reg.cpp intel/compiler: Use unreachable instead of assert(!"...") 2025-03-13 20:11:10 +00:00
brw_reg.h brw: add new helper for immediate integer register with type 2025-06-22 10:55:24 +00:00
brw_reg_allocate.cpp brw: Fix MAD instruction usage in spilling logic 2025-06-06 15:31:50 +00:00
brw_reg_type.c brw: Add BRW_TYPE_BF for bfloat16 2025-03-25 05:23:37 +00:00
brw_reg_type.h brw: Add BRW_TYPE_BF for bfloat16 2025-03-25 05:23:37 +00:00
brw_rt.h intel/compiler: Use #pragma once instead of header guards 2024-12-11 19:47:44 +00:00
brw_schedule_instructions.cpp brw: Use live->max_vgrf_size in pre-RA scheduling 2025-04-11 20:34:51 +00:00
brw_shader.cpp intel/debug: shader dump filter 2025-05-23 19:57:02 +00:00
brw_shader.h intel: introduce new VUE layout for separate compiled shader with mesh 2025-05-08 06:48:35 +00:00
brw_simd_selection.cpp intel/brw/xe3+: Optimize CS/TASK/MESH compile time optimistically assuming SIMD32. 2025-01-29 23:39:32 +00:00
brw_spirv.c nir/peephole_select: add options struct 2025-02-20 21:59:16 +00:00
brw_thread_payload.cpp brw: Embed at_end() inside brw_builder(brw_shader *) constructor 2025-03-06 23:33:38 +00:00
brw_thread_payload.h intel/brw: Rename fs_visitor to brw_shader 2025-02-11 09:13:28 +00:00
brw_validate.cpp brw: introduce MEMORY_LOGICAL_ADDRESS_OFFSET to encode address offsets 2025-06-22 10:55:24 +00:00
brw_vue_map.c intel/compiler: use ffsll instead of ffsl in brw_vue_map.c 2025-05-11 00:50:21 +02:00
brw_workaround.cpp brw: fix Wa_22013689345 emission 2025-04-10 16:44:28 +00:00
intel_gfx_ver_enum.h intel/compiler: Use #pragma once instead of header guards 2024-12-11 19:47:44 +00:00
intel_nir.c intel/compiler: Use nir_split_conversions() 2025-04-07 17:45:21 -05:00
intel_nir.h anv: lower input vertices for TCS unconditionally 2025-05-08 06:48:34 +00:00
intel_nir_blockify_uniform_loads.c intel: replace RANGE_BASE by BASE for uniform block loads 2025-06-22 10:55:23 +00:00
intel_nir_clamp_image_1d_2d_array_sizes.c treewide: use nir_metadata_control_flow 2024-06-17 16:28:14 -04:00
intel_nir_clamp_per_vertex_loads.c anv: lower input vertices for TCS unconditionally 2025-05-08 06:48:34 +00:00
intel_nir_lower_non_uniform_barycentric_at_sample.c intel: switch to nir_metadata_divergence 2025-02-13 10:08:43 +00:00
intel_nir_lower_non_uniform_resource_intel.c treewide: use nir_metadata_control_flow 2024-06-17 16:28:14 -04:00
intel_nir_lower_printf.c nir: drop printf_base_identifier 2025-02-05 20:33:15 +00:00
intel_nir_lower_shading_rate_output.c treewide: use nir_metadata_control_flow 2024-06-17 16:28:14 -04:00
intel_nir_lower_sparse.c treewide: use nir_metadata_control_flow 2024-06-17 16:28:14 -04:00
intel_nir_opt_peephole_ffma.c treewide: use nir_metadata_control_flow 2024-06-17 16:28:14 -04:00
intel_nir_opt_peephole_imul32x16.c treewide: use nir_metadata_control_flow 2024-06-17 16:28:14 -04:00
intel_nir_tcs_workarounds.c treewide: Switch to nir_progress 2025-02-26 15:19:53 +00:00
intel_shader_enums.h brw/anv: add provoking vertex to fs_msaa_flags 2025-05-20 20:57:58 +00:00
meson.build brw: run the nir_opt_offsets pass and set the maximum offset size 2025-06-22 10:55:24 +00:00
test_eu_compact.cpp intel/brw: Rename brw_inst_* helpers to brw_eu_inst_* 2024-12-30 17:16:15 +00:00
test_eu_validate.cpp brw: Allow DPAS with BF on Gfx125 2025-04-14 18:23:43 +00:00
test_helpers.cpp brw: Simplify the test code for brw passes 2025-03-13 17:43:17 +00:00
test_helpers.h brw: Simplify the test code for brw passes 2025-03-13 17:43:17 +00:00
test_insert_load_reg.cpp brw: Add passes to generate and lower load_reg 2025-04-04 06:45:02 +00:00
test_lower_scoreboard.cpp brw: Fix invalid memory access in scoreboard test 2025-04-05 22:58:23 -07:00
test_opt_algebraic.cpp brw/algebraic: Don't optimize float SEL.CMOD to MOV 2025-04-15 23:59:31 +00:00
test_opt_cmod_propagation.cpp brw/cmod: Don't propagate from CMP to possible Inf + (-Inf) 2025-04-28 19:44:23 +00:00
test_opt_combine_constants.cpp brw: Add brw_builder::uniform() 2025-04-04 23:07:21 +00:00
test_opt_copy_propagation.cpp brw: Simplify the test code for brw passes 2025-03-13 17:43:17 +00:00
test_opt_cse.cpp brw: Simplify the test code for brw passes 2025-03-13 17:43:17 +00:00
test_opt_register_coalesce.cpp brw: don't generate invalid instructions 2025-06-04 06:08:26 +00:00
test_opt_saturate_propagation.cpp brw/sat: Eliminate non-defs saturate propagation 2025-04-04 06:45:02 +00:00
test_simd_selection.cpp intel: Switch uint64_t intel_debug to a bitset 2025-04-22 23:09:26 +00:00
test_vf_float_conversions.cpp