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brw: introduce MEMORY_LOGICAL_ADDRESS_OFFSET to encode address offsets

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Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35252>
This commit is contained in:
Rohan Garg 2024-10-21 16:40:51 +02:00 • committed by Marge Bot
parent d5a58364b1
commit 937d37f0b1
5 changed files with 36 additions and 1 deletions
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3
src/intel/compiler/brw_eu_defines.h
View file

@ -686,6 +686,9 @@ enum memory_logical_srcs {
/** Coordinate/address/offset for where to access memory */
MEMORY_LOGICAL_ADDRESS,
/** Xe2+: offset for where to access memory (as UD immediate) */
MEMORY_LOGICAL_ADDRESS_OFFSET,
/** Dimensionality of the "address" source (as UD immediate) */
MEMORY_LOGICAL_COORD_COMPONENTS,

4
src/intel/compiler/brw_from_nir.cpp
View file

@ -4701,6 +4701,7 @@ brw_from_nir_emit_cs_intrinsic(nir_to_brw_state &ntb,
srcs[MEMORY_LOGICAL_DATA_SIZE] = brw_imm_ud(LSC_DATA_SIZE_D32);
srcs[MEMORY_LOGICAL_COMPONENTS] = brw_imm_ud(3);
srcs[MEMORY_LOGICAL_FLAGS] = brw_imm_ud(0);
srcs[MEMORY_LOGICAL_ADDRESS_OFFSET] = brw_imm_d(0);
brw_inst *inst =
bld.emit(SHADER_OPCODE_MEMORY_LOAD_LOGICAL,
@ -6978,6 +6979,9 @@ brw_from_nir_emit_memory_access(nir_to_brw_state &ntb,
brw_imm_ud(include_helpers ? MEMORY_FLAG_INCLUDE_HELPERS : 0);
/* DATA0 and DATA1 are handled below */
/* Set the default address offset to 0 */
srcs[MEMORY_LOGICAL_ADDRESS_OFFSET] = brw_imm_d(0);
switch (instr->intrinsic) {
case nir_intrinsic_bindless_image_load:
case nir_intrinsic_bindless_image_store:

9
src/intel/compiler/brw_lower_logical_sends.cpp
View file

@ -1491,6 +1491,11 @@ lower_lsc_memory_logical_send(const brw_builder &bld, brw_inst *inst)
const enum lsc_addr_size addr_size = lsc_addr_size_for_type(addr.type);
const brw_reg base_offset =
retype(inst->src[MEMORY_LOGICAL_ADDRESS_OFFSET], BRW_TYPE_UD);
/* TODO: setup the offset */
assert(base_offset.ud == 0);
brw_reg payload = addr;
if (addr.file != VGRF || !addr.is_contiguous()) {
@ -1651,6 +1656,7 @@ lower_hdc_memory_logical_send(const brw_builder &bld, brw_inst *inst)
assert(inst->src[MEMORY_LOGICAL_COORD_COMPONENTS].file == IMM);
assert(inst->src[MEMORY_LOGICAL_DATA_SIZE].file == IMM);
assert(inst->src[MEMORY_LOGICAL_FLAGS].file == IMM);
assert(inst->src[MEMORY_LOGICAL_ADDRESS_OFFSET].file == IMM);
/* Get the logical send arguments. */
const enum lsc_opcode op = (lsc_opcode)inst->src[MEMORY_LOGICAL_OPCODE].ud;
@ -1672,6 +1678,9 @@ lower_hdc_memory_logical_send(const brw_builder &bld, brw_inst *inst)
const brw_reg data1 = inst->src[MEMORY_LOGICAL_DATA1];
const bool has_side_effects = inst->has_side_effects();
const bool has_dest = inst->dst.file != BAD_FILE && !inst->dst.is_null();
const brw_reg base_offset =
retype(inst->src[MEMORY_LOGICAL_ADDRESS_OFFSET], BRW_TYPE_UD);
assert(base_offset.ud == 0);
/* Don't predicate scratch writes on the sample mask. Otherwise,
* FS helper invocations would load undefined values from scratch memory.

7
src/intel/compiler/brw_print.cpp
View file

@ -322,7 +322,9 @@ static bool
print_memory_logical_source(FILE *file, const brw_inst *inst, unsigned i)
{
if (inst->is_control_source(i)) {
assert(inst->src[i].file == IMM && inst->src[i].type == BRW_TYPE_UD);
assert(inst->src[i].file == IMM &&
(inst->src[i].type == BRW_TYPE_UD ||
inst->src[i].type == BRW_TYPE_D));
assert(!inst->src[i].negate);
assert(!inst->src[i].abs);
}
@ -353,6 +355,9 @@ print_memory_logical_source(FILE *file, const brw_inst *inst, unsigned i)
case MEMORY_LOGICAL_ADDRESS:
fprintf(file, " addr: ");
return false;
case MEMORY_LOGICAL_ADDRESS_OFFSET:
fprintf(file, " offset: ");
return false;
case MEMORY_LOGICAL_COORD_COMPONENTS:
fprintf(file, " coord_comps:");
return false;

14
src/intel/compiler/brw_validate.cpp
View file

@ -94,6 +94,12 @@ is_ud_imm(const brw_reg &reg)
return reg.file == IMM && reg.type == BRW_TYPE_UD;
}
static inline bool
is_d_imm(const brw_reg &reg)
{
return reg.file == IMM && reg.type == BRW_TYPE_D;
}
static void
validate_memory_logical(const brw_shader &s, const brw_inst *inst)
{
@ -107,6 +113,7 @@ validate_memory_logical(const brw_shader &s, const brw_inst *inst)
fsv_assert(is_ud_imm(inst->src[MEMORY_LOGICAL_DATA_SIZE]));
fsv_assert(is_ud_imm(inst->src[MEMORY_LOGICAL_COMPONENTS]));
fsv_assert(is_ud_imm(inst->src[MEMORY_LOGICAL_FLAGS]));
fsv_assert(is_d_imm(inst->src[MEMORY_LOGICAL_ADDRESS_OFFSET]));
enum lsc_opcode op = (enum lsc_opcode) inst->src[MEMORY_LOGICAL_OPCODE].ud;
enum memory_flags flags = (memory_flags)inst->src[MEMORY_LOGICAL_FLAGS].ud;
@ -157,6 +164,13 @@ validate_memory_logical(const brw_shader &s, const brw_inst *inst)
if (inst->dst.file != BAD_FILE)
fsv_assert(brw_type_size_bytes(inst->dst.type) == data_size_B);
/** TGM messages cannot have a base offset */
if (mode == MEMORY_MODE_TYPED)
fsv_assert(inst->src[MEMORY_LOGICAL_ADDRESS_OFFSET].d == 0);
/* Offset must be DWord aligned */
fsv_assert((inst->src[MEMORY_LOGICAL_ADDRESS_OFFSET].d % 4) == 0);
switch (inst->opcode) {
case SHADER_OPCODE_MEMORY_LOAD_LOGICAL:
fsv_assert(op == LSC_OP_LOAD || op == LSC_OP_LOAD_CMASK ||