intel/brw: Simplify @file annotations

Doxygen documentation says

> If the file name is omitted (i.e. the line after \file is left
> blank) then the documentation block that contains the \file command will
> belong to the file it is located in.

so we can omit the filename itself when using the annotation.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30168>

src/intel/compiler/brw_cfg.cpp

@@ -29,7 +29,7 @@
 #include "util/u_dynarray.h"
 #include "brw_fs.h"
 
-/** @file brw_cfg.cpp
+/** @file
  *
  * Walks the shader instructions generated and creates a set of basic
  * blocks with successor/predecessor edges connecting them.

src/intel/compiler/brw_dead_control_flow.cpp

@@ -21,7 +21,7 @@
  * IN THE SOFTWARE.
  */
 
-/** @file brw_dead_control_flow.cpp
+/** @file
  *
  * This file implements the dead control flow elimination optimization pass.
  */

src/intel/compiler/brw_debug_recompile.c

@@ -21,7 +21,7 @@
  */
 
 /**
- * @file brw_debug_recompiles.c
+ * @file
  */
 
 #include <stdio.h>

src/intel/compiler/brw_eu_compact.c

@@ -21,7 +21,7 @@
  * IN THE SOFTWARE.
  */
 
-/** @file brw_eu_compact.c
+/** @file
  *
  * Instruction compaction is a feature of G45 and newer hardware that allows
  * for a smaller instruction encoding.

src/intel/compiler/brw_eu_validate.c

@@ -21,7 +21,7 @@
  * IN THE SOFTWARE.
  */
 
-/** @file brw_eu_validate.c
+/** @file
  *
  * This file implements a pass that validates shader assembly.
  *

src/intel/compiler/brw_fs.cpp

@@ -21,7 +21,7 @@
  * IN THE SOFTWARE.
  */
 
-/** @file brw_fs.cpp
+/** @file
  *
  * This file drives the GLSL IR -> LIR translation, contains the
  * optimizations on the LIR, and drives the generation of native code

src/intel/compiler/brw_fs_bank_conflicts.cpp

@@ -21,7 +21,7 @@
  * IN THE SOFTWARE.
  */
 
-/** @file brw_fs_bank_conflicts.cpp
+/** @file
  *
  * This file contains a GRF bank conflict mitigation pass.  The pass is
  * intended to be run after register allocation and works by rearranging the

src/intel/compiler/brw_fs_cmod_propagation.cpp

@@ -25,7 +25,7 @@
 #include "brw_cfg.h"
 #include "brw_eu.h"
 
-/** @file brw_fs_cmod_propagation.cpp
+/** @file
  *
  * Implements a pass that propagates the conditional modifier from a CMP x 0.0
  * instruction into the instruction that generated x. For instance, in this

src/intel/compiler/brw_fs_combine_constants.cpp

@@ -21,7 +21,7 @@
  * IN THE SOFTWARE.
  */
 
-/** @file brw_fs_combine_constants.cpp
+/** @file
  *
  * This file contains the opt_combine_constants() pass that runs after the
  * regular optimization loop. It passes over the instruction list and promotes

src/intel/compiler/brw_fs_copy_propagation.cpp

@@ -21,7 +21,7 @@
  * IN THE SOFTWARE.
  */
 
-/** @file brw_fs_copy_propagation.cpp
+/** @file
  *
  * Support for global copy propagation in two passes: A local pass that does
  * intra-block copy (and constant) propagation, and a global pass that uses

src/intel/compiler/brw_fs_cse.cpp

@@ -28,7 +28,7 @@
 #include "brw_fs_builder.h"
 #include "brw_cfg.h"
 
-/** @file brw_fs_cse.cpp
+/** @file
  *
  * Support for SSA-based global Common Subexpression Elimination (CSE).
  */

src/intel/compiler/brw_fs_dead_code_eliminate.cpp

@@ -25,7 +25,7 @@
 #include "brw_fs_live_variables.h"
 #include "brw_cfg.h"
 
-/** @file brw_fs_dead_code_eliminate.cpp
+/** @file
  *
  * Dataflow-aware dead code elimination.
  *

src/intel/compiler/brw_fs_generator.cpp

@@ -21,7 +21,7 @@
  * IN THE SOFTWARE.
  */
 
-/** @file brw_fs_generator.cpp
+/** @file
  *
  * This file supports generating code from the FS LIR to the actual
  * native instructions.

src/intel/compiler/brw_fs_live_variables.cpp

@@ -32,7 +32,7 @@ using namespace brw;
 
 #define MAX_INSTRUCTION (1 << 30)
 
-/** @file brw_fs_live_variables.cpp
+/** @file
  *
  * Support for calculating liveness information about virtual GRFs.
  *

src/intel/compiler/brw_fs_register_coalesce.cpp

@@ -21,7 +21,7 @@
  * IN THE SOFTWARE.
  */
 
-/** @file brw_fs_register_coalesce.cpp
+/** @file
  *
  * Implements register coalescing: Checks if the two registers involved in a
  * raw move don't interfere, in which case they can both be stored in the same

src/intel/compiler/brw_fs_saturate_propagation.cpp

@@ -27,7 +27,7 @@
 
 using namespace brw;
 
-/** @file brw_fs_saturate_propagation.cpp
+/** @file
  *
  * Implements a pass that propagates the SAT modifier from a MOV.SAT into the
  * instruction that produced the source of the MOV.SAT, thereby allowing the

src/intel/compiler/brw_fs_scoreboard.cpp

@@ -21,7 +21,7 @@
  * IN THE SOFTWARE.
  */
 
-/** @file brw_fs_scoreboard.cpp
+/** @file
  *
  * Gfx12+ hardware lacks the register scoreboard logic that used to guarantee
  * data coherency between register reads and writes in previous generations.

src/intel/compiler/brw_fs_sel_peephole.cpp

@@ -25,7 +25,7 @@
 #include "brw_fs_builder.h"
 #include "brw_cfg.h"
 
-/** @file brw_fs_sel_peephole.cpp
+/** @file
  *
  * This file contains the opt_peephole_sel() optimization pass that replaces
  * MOV instructions to the same destination in the "then" and "else" bodies of

src/intel/compiler/brw_fs_validate.cpp

@@ -21,7 +21,7 @@
  * IN THE SOFTWARE.
  */
 
-/** @file brw_fs_validate.cpp
+/** @file
  *
  * Implements a pass that validates various invariants of the IR.  The current
  * pass only validates that GRF's uses are sane.  More can be added later.

src/intel/compiler/brw_fs_visitor.cpp

@@ -21,7 +21,7 @@
  * IN THE SOFTWARE.
  */
 
-/** @file brw_fs_visitor.cpp
+/** @file
  *
  * This file supports generating the FS LIR from the GLSL IR.  The LIR
  * makes it easier to do backend-specific optimizations than doing so

src/intel/compiler/brw_inst.h

@@ -22,7 +22,7 @@
  */
 
 /**
- * @file brw_inst.h
+ * @file
  *
  * A representation of i965 EU assembly instructions, with helper methods to
  * get and set various fields.  This is the actual hardware format.

src/intel/compiler/brw_lower_logical_sends.cpp

@@ -22,7 +22,7 @@
  */
 
 /**
- * @file brw_lower_logical_sends.cpp
+ * @file
  */
 
 #include "brw_eu.h"

src/intel/compiler/brw_predicated_break.cpp

@@ -25,7 +25,7 @@
 
 using namespace brw;
 
-/** @file brw_predicated_break.cpp
+/** @file
  *
  * Loops are often structured as
  *

src/intel/compiler/brw_reg.h

@@ -29,7 +29,7 @@
   *   Keith Whitwell <keithw@vmware.com>
   */
 
-/** @file brw_reg.h
+/** @file
  *
  * This file defines struct brw_reg, which is our representation for EU
  * registers.  They're not a hardware specific format, just an abstraction

src/intel/compiler/brw_schedule_instructions.cpp

@@ -33,7 +33,7 @@
 
 using namespace brw;
 
-/** @file brw_fs_schedule_instructions.cpp
+/** @file
  *
  * List scheduling of FS instructions.
  *

src/intel/compiler/brw_vue_map.c

@@ -22,7 +22,7 @@
  */
 
 /**
- * @file brw_vue_map.c
+ * @file
  *
  * This file computes the "VUE map" for a (non-fragment) shader stage, which
  * describes the layout of its output varyings.  The VUE map is used to match