anv: lower input vertices for TCS unconditionally

Take the opportunity to reuse the backend pass.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34109>

src/intel/compiler/brw_compile_tcs.cpp

@@ -210,7 +210,7 @@ brw_compile_tcs(const struct brw_compiler *compiler,
    brw_nir_lower_tcs_outputs(nir, &vue_prog_data->vue_map,
                              key->_tes_primitive_mode);
    if (key->input_vertices > 0)
-      intel_nir_lower_patch_vertices_in(nir, key->input_vertices);
+      intel_nir_lower_patch_vertices_in(nir, key->input_vertices, NULL, NULL);
 
    brw_postprocess_nir(nir, compiler, debug_enabled,
                        key->base.robust_flags);

src/intel/compiler/elk/elk_vec4_tcs.cpp

@@ -385,7 +385,7 @@ elk_compile_tcs(const struct elk_compiler *compiler,
    if (key->quads_workaround)
       intel_nir_apply_tcs_quads_workaround(nir);
    if (key->input_vertices > 0)
-      intel_nir_lower_patch_vertices_in(nir, key->input_vertices);
+      intel_nir_lower_patch_vertices_in(nir, key->input_vertices, NULL, NULL);
 
    elk_postprocess_nir(nir, compiler, debug_enabled,
                        key->base.robust_flags);

src/intel/compiler/intel_nir.h

@@ -13,6 +13,8 @@ extern "C" {
 
 struct intel_device_info;
 
+
+
 void intel_nir_apply_tcs_quads_workaround(nir_shader *nir);
 bool brw_nir_rebase_const_offset_ubo_loads(nir_shader *shader);
 bool intel_nir_blockify_uniform_loads(nir_shader *shader,
@@ -23,7 +25,10 @@ bool intel_nir_cleanup_resource_intel(nir_shader *shader);
 
 bool intel_nir_lower_non_uniform_barycentric_at_sample(nir_shader *nir);
 bool intel_nir_lower_non_uniform_resource_intel(nir_shader *shader);
-bool intel_nir_lower_patch_vertices_in(nir_shader *shader, unsigned input_vertices);
+bool intel_nir_lower_patch_vertices_in(nir_shader *shader,
+                                       unsigned input_vertices,
+                                       nir_lower_instr_cb cb,
+                                       void *data);
 bool intel_nir_lower_shading_rate_output(nir_shader *nir);
 bool intel_nir_lower_sparse_intrinsics(nir_shader *nir);
 

src/intel/compiler/intel_nir_clamp_per_vertex_loads.c

@@ -81,6 +81,12 @@ intel_nir_clamp_per_vertex_loads(nir_shader *shader)
    return ret;
 }
 
+struct lower_patch_vertices_state {
+   unsigned input_vertices;
+   nir_lower_instr_cb cb;
+   void *data;
+};
+
 static bool
 lower_patch_vertices_instr(nir_builder *b, nir_intrinsic_instr *intrin,
                            void *cb_data)
@@ -88,19 +94,31 @@ lower_patch_vertices_instr(nir_builder *b, nir_intrinsic_instr *intrin,
    if (intrin->intrinsic != nir_intrinsic_load_patch_vertices_in)
       return false;
 
-   unsigned *input_vertices = cb_data;
+   struct lower_patch_vertices_state *state = cb_data;
 
    b->cursor = nir_before_instr(&intrin->instr);
 
-   nir_def_rewrite_uses(&intrin->def, nir_imm_int(b, *input_vertices));
+   nir_def *val =
+      state->input_vertices ?
+      nir_imm_int(b, state->input_vertices) :
+      state->cb(b, &intrin->instr, state->data);
+   nir_def_rewrite_uses(&intrin->def, val);
 
    return true;
 }
 
 bool
-intel_nir_lower_patch_vertices_in(nir_shader *shader, unsigned input_vertices)
+intel_nir_lower_patch_vertices_in(nir_shader *shader,
+                                  unsigned input_vertices,
+                                  nir_lower_instr_cb cb,
+                                  void *data)
 {
+   assert(input_vertices != 0 || cb != NULL);
+   struct lower_patch_vertices_state state = {
+      .input_vertices = input_vertices,
+      .cb = cb,
+      .data = data,
+   };
    return nir_shader_intrinsics_pass(shader, lower_patch_vertices_instr,
-                                       nir_metadata_control_flow,
-                                       &input_vertices);
+                                     nir_metadata_control_flow, &state);
 }

src/intel/vulkan/anv_nir.h

@@ -69,8 +69,6 @@ bool anv_check_for_primitive_replication(struct anv_device *device,
                                          nir_shader **shaders,
                                          uint32_t view_mask);
 
-bool anv_nir_lower_load_patch_vertices_in(nir_shader *shader);
-
 bool anv_nir_lower_multiview(nir_shader *shader, uint32_t view_mask,
                              bool use_primitive_replication);
 

src/intel/vulkan/anv_nir_lower_load_patch_vertices_in.c

@@ -1,61 +0,0 @@
-/*
- * Copyright © 2023 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- */
-
-/**
- * This file implements the lowering required for
- * VK_EXT_extended_dynamic_state2 extendedDynamicState2PatchControlPoints.
- *
- * When VK_DYNAMIC_STATE_PATCH_CONTROL_POINTS_EXT is set on a pipeline, we
- * need to compile the TCS shader assuming the max (32) number of control
- * points. The actually value is provided through push constants.
- */
-
-#include "anv_nir.h"
-#include "nir_builder.h"
-
-#define sizeof_field(type, field) sizeof(((type *)0)->field)
-
-static bool
-lower_patch_vertices_in_instr(nir_builder *b, nir_intrinsic_instr *load,
-                              UNUSED void *_data)
-{
-   if (load->intrinsic != nir_intrinsic_load_patch_vertices_in)
-      return false;
-
-   b->cursor = nir_before_instr(&load->instr);
-
-   nir_def_rewrite_uses(
-      &load->def,
-      anv_load_driver_uniform(b, 1, gfx.tcs_input_vertices));
-   nir_instr_remove(&load->instr);
-
-   return true;
-}
-
-bool
-anv_nir_lower_load_patch_vertices_in(nir_shader *shader)
-{
-   return nir_shader_intrinsics_pass(shader, lower_patch_vertices_in_instr,
-                                       nir_metadata_control_flow,
-                                       NULL);
-}

src/intel/vulkan/anv_pipeline.c

@@ -946,6 +946,12 @@ lower_non_tg4_non_uniform_offsets(const nir_tex_instr *tex,
    return false;
 }
 
+static nir_def *
+build_tcs_input_vertices(nir_builder *b, nir_instr *instr, void *data)
+{
+   return anv_load_driver_uniform(b, 1, gfx.tcs_input_vertices);
+}
+
 static void
 anv_pipeline_lower_nir(struct anv_pipeline *pipeline,
                        void *mem_ctx,
@@ -996,9 +1002,11 @@ anv_pipeline_lower_nir(struct anv_pipeline *pipeline,
    /* The patch control points are delivered through a push constant when
     * dynamic.
     */
-   if (nir->info.stage == MESA_SHADER_TESS_CTRL &&
-       stage->key.tcs.input_vertices == 0)
-      NIR_PASS(_, nir, anv_nir_lower_load_patch_vertices_in);
+   if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
+      NIR_PASS(_, nir, intel_nir_lower_patch_vertices_in,
+               stage->key.tcs.input_vertices,
+               build_tcs_input_vertices, NULL);
+   }
 
    nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
 

src/intel/vulkan/meson.build

@@ -191,7 +191,6 @@ libanv_files = files(
   'anv_nir_apply_pipeline_layout.c',
   'anv_nir_compute_push_layout.c',
   'anv_nir_lower_multiview.c',
-  'anv_nir_lower_load_patch_vertices_in.c',
   'anv_nir_lower_ubo_loads.c',
   'anv_nir_lower_resource_intel.c',
   'anv_nir_push_descriptor_analysis.c',